starting wfg

radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv

@@ -0,0 +1,159 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module gen_ofdm # (
+    parameter integer AXI_ADDR_WIDTH	= 32,
+    parameter integer AXI_DATA_WIDTH	= 32	
+)
+(
+    input  wire        clk,
+    input  wire        reset,
+    axi4l_intf.slave   ctrl_if,
+
+	input  wire 	   start_pulse,
+
+    output wire [127:0] iq_out,
+	output wire         iq_out_valid
+);
+
+// ------------------------------
+// AXIL Decode
+// ------------------------------
+wire [AXI_ADDR_WIDTH-1 : 0]		raddr;
+wire [AXI_ADDR_WIDTH-1 : 0]		waddr;
+wire 						    rden;
+wire 						    wren;
+wire [AXI_DATA_WIDTH-1 : 0]		wdata;
+reg [AXI_DATA_WIDTH-1 : 0]		rdata;
+
+
+axil_slave 
+# (
+	.DATA_WIDTH(AXI_DATA_WIDTH),
+	.ADDR_WIDTH(AXI_ADDR_WIDTH)
+) axil_slave_i 
+(
+	// AXIL Slave
+	.S_AXI_ACLK(ctrl_if.clk),
+	.S_AXI_ARESETN(ctrl_if.resetn),
+	.S_AXI_AWADDR(ctrl_if.awaddr),
+	.S_AXI_AWPROT(ctrl_if.awprot),
+	.S_AXI_AWVALID(ctrl_if.awvalid),
+	.S_AXI_AWREADY(ctrl_if.awready),
+	.S_AXI_WDATA(ctrl_if.wdata),
+	.S_AXI_WSTRB(ctrl_if.wstrb),
+	.S_AXI_WVALID(ctrl_if.wvalid),
+	.S_AXI_WREADY(ctrl_if.wready),
+	.S_AXI_BRESP(ctrl_if.bresp),
+	.S_AXI_BVALID(ctrl_if.bvalid),
+	.S_AXI_BREADY(ctrl_if.bready),
+	.S_AXI_ARADDR(ctrl_if.araddr),
+	.S_AXI_ARPROT(ctrl_if.arprot),
+	.S_AXI_ARVALID(ctrl_if.arvalid),
+	.S_AXI_ARREADY(ctrl_if.arready),
+	.S_AXI_RDATA(ctrl_if.rdata),
+	.S_AXI_RRESP(ctrl_if.rresp),
+	.S_AXI_RVALID(ctrl_if.rvalid),
+	.S_AXI_RREADY(ctrl_if.rready),	
+	
+	.raddr(raddr),
+	.waddr(waddr),
+	.wren(wren),
+    .rden(rden),
+	.wdata(wdata),
+	.rdata(rdata)
+);
+
+// ------------------------------
+// Config Registers
+// ------------------------------
+reg [31:0]  reg_ctrl;
+reg [31:0]  reg_freq;
+reg [31:0]  reg_phase;
+reg [31:0]  reg_chips;
+
+always @ (posedge ctrl_if.clk) begin
+    if (~ctrl_if.resetn) begin
+        reg_ctrl <= 0;
+        reg_freq <= 0;
+        reg_phase <= 0;
+    end else begin
+        if (wren) begin
+            if (waddr[11:0] == 'h000) begin
+                reg_ctrl <= wdata;
+            end
+            if (waddr[11:0] == 'h004) begin
+                reg_freq <= wdata;
+            end
+            if (waddr[11:0] == 'h008) begin
+                reg_phase <= wdata;
+            end 
+            if (waddr[11:0] == 'h00C) begin
+                reg_chips <= wdata;
+            end      
+            // if (waddr[11:0] == 'h010) begin
+            //     reg_phase <= wdata;
+            // end      						                       
+        end
+    end
+end
+
+wire [15:0] n_samp_chip = reg_chips[15:0];
+wire [15:0] n_chip = reg_chips[31:16];
+
+
+// ------------------------------
+// Bla
+// ------------------------------
+reg [24:0] pulse_cnt;
+reg [15:0] chip_cnt;
+reg [15:0] chip_ind;
+reg pulse_active;
+reg start_of_pulse;
+
+always @ (posedge clk) begin
+	if (reset) begin
+		chip_cnt <= 0;
+		chip_ind <= 0;
+		pulse_active <= 1'b0;
+		start_of_pulse <= 1'b0;
+	end else begin
+		start_of_pulse <= 1'b0;
+		if (start_pulse) begin
+			chip_cnt <= 0;
+			chip_ind <= 0;
+			pulse_active <= 1'b1;
+			start_of_pulse <= 1'b1;
+		end
+
+		if (pulse_active) begin
+			chip_cnt <= chip_cnt + 1;
+			if (chip_cnt == n_samp_chip - 1) begin
+				chip_cnt <= 0;
+				chip_ind <= chip_ind + 1;
+				if (chip_ind == n_chip - 1) begin
+					chip_ind <= 0;
+					pulse_active = 1'b0;
+				end
+			end
+		end
+	end
+end
+
+
+
+gen_sine gen_sine_i (
+    .clk(clk),
+    .reset(reset),  
+    .set_phase(start_of_pulse),  
+	.valid(pulse_active),
+    .phase(reg_phase),
+    .frequency(reg_freq),
+    .iq_out(iq_out),
+	.iq_out_valid(iq_out_valid)
+);
+
+endmodule
+`resetall
+

radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv

@@ -0,0 +1,72 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Generates 4 output samples in parallel
+// Samples are 16 bit I and 16 bit Q, 32 bits per sample
+
+module gen_sine
+(
+    input  wire        clk,
+    input  wire        reset,
+    input  wire        set_phase,
+    input  wire        valid,
+    input  wire [31:0] phase,
+    input  wire [31:0] frequency,
+
+    output wire [127:0] iq_out,
+    output wire         iq_out_valid
+);
+
+reg        set_phase_q;
+reg        valid_q;
+reg        valid_q2;
+reg [31:0] phase_q;
+reg [31:0] frequency_q;
+reg [127:0] iq_out_i;
+
+always @ (posedge clk) begin
+    set_phase_q <= set_phase;
+    phase_q <= phase;
+    frequency_q <= frequency;
+    valid_q <= valid;
+    valid_q2 <= valid_q;
+end
+
+genvar i;
+generate
+    for (i = 0; i < 4; i = i + 1) begin
+
+        reg [31:0] phase_accum;
+        
+        always @ (posedge clk) begin
+            if (reset) begin
+                phase_accum <= 0;
+            end else if (valid_q) begin
+                if (set_phase_q) begin
+                    phase_accum <= phase_q + i*frequency_q;
+                end else begin
+                    phase_accum <= phase_accum + 4*frequency_q;
+                end
+            end
+        end
+
+
+        wire [39:0] cordic_phase_in = {{8{phase_accum[31]}}, phase_accum};
+
+        wfg_cordic wfg_cordic_i (
+            .aclk(clk),
+            .s_axis_phase_tvalid(valid_q2),  
+            .s_axis_phase_tdata(cordic_phase_in),  
+            .m_axis_dout_tvalid(iq_out_valid),
+            .m_axis_dout_tdata(iq_out_i[i*32+31:i*32])  
+        );
+                
+    end
+endgenerate  
+
+assign iq_out = iq_out_i;
+
+endmodule
+`resetall
+