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not sure why build isnt working for chris

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This commit is contained in:
bkiedinger@gmail.com
2025-08-01 17:45:26 -05:00
parent 707e9f82a4
commit 3648531294
14 changed files with 81 additions and 54 deletions
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48
vitis/bootloader/_ide/bitstream/top.mmi
View File

@@ -13,49 +13,49 @@
<AddressSpace Name="microblaze_bd_i_microblaze_0.microblaze_bd_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="32767">
<AddressSpaceRange Name="microblaze_bd_i_microblaze_0.microblaze_bd_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="32767" CoreMemory_Width="0" MemoryType="RAM_SP" MemoryConfiguration="">
<BusBlock>
<BitLane MemType="RAMB36" Placement="X5Y36" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y9" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="7" LSB="4"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X5Y35" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y10" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="3" LSB="0"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y36" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y14" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="15" LSB="12"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y35" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y13" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="11" LSB="8"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y40" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y6" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="23" LSB="20"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y39" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y5" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="19" LSB="16"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y38" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y11" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="31" LSB="28"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y37" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y7" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="27" LSB="24"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
@@ -69,97 +69,97 @@
<AddressSpace Name="microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_microblaze_I.microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_dlmb_cntlr" Begin="0" End="65535">
<AddressSpaceRange Name="microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_microblaze_I.microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_dlmb_cntlr" Begin="0" End="65535" CoreMemory_Width="0" MemoryType="RAM_SP" MemoryConfiguration="">
<BusBlock>
<BitLane MemType="RAMB36" Placement="X0Y8" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X2Y24" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="7" LSB="6"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y9" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X2Y25" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="5" LSB="4"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y7" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y24" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="3" LSB="2"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y10" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y22" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="1" LSB="0"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y20" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X0Y25" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="15" LSB="14"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y24" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X0Y24" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="13" LSB="12"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X2Y20" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y26" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="11" LSB="10"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y21" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y25" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="9" LSB="8"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y4" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y19" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="23" LSB="22"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y23" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X2Y19" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="21" LSB="20"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y24" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y17" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="19" LSB="18"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y25" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X0Y20" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="17" LSB="16"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y22" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X2Y21" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="31" LSB="30"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y22" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X0Y18" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="29" LSB="28"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y5" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X0Y22" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="27" LSB="26"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y6" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y18" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="25" LSB="24"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>

2
vitis/bootloader/_ide/hwspec.checksum
View File

@@ -1 +1 @@
308456516
2843589716

2
vitis/bootloader/bootloader.prj
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="bootloader" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/bootloader" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="bootloader_system" sysConfig="top" runtime="cpp" cpu="standalone_microblaze_0" cpuInstance="microblaze_0" os="standalone" mssSignature="5cf4b93eb4839ad64096fe0b93be55b5">
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="bootloader" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/bootloader" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="bootloader_system" sysConfig="top" runtime="cpp" cpu="standalone_microblaze_0" cpuInstance="microblaze_0" os="standalone" mssSignature="08fc47d054e6efb8b129bdcd2742c9c1">
<configuration name="Debug" id="xilinx.gnu.mb.exe.debug.787148227">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>