bkiedinger/castelion_radar_alinx_kintex
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renamed system verilog files to have .sv extensions

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This commit is contained in:
bkiedinger@gmail.com
2025-11-12 21:33:16 -06:00
parent d9a14af015
commit 5923ec0831
7 changed files with 21 additions and 21 deletions
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0
radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.v → radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.sv
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0
radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.v → radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.sv
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0
radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v → radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.sv
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2
radar_alinx_kintex.srcs/sources_1/hdl/top.v → radar_alinx_kintex.srcs/sources_1/hdl/top.sv
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@@ -948,7 +948,7 @@ module top #
wire [127:0] iq_out;
wire iq_out_valid;
gen_ofdm dut (
gen_ofdm waveform_gen_i (
.clk(jesd_core_clk),
.reset(1'b0),

0
radar_alinx_kintex.srcs/sources_1/hdl/util_reg.v → radar_alinx_kintex.srcs/sources_1/hdl/util_reg.sv
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0
radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.v → radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.sv
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40
radar_alinx_kintex.xpr
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@@ -458,15 +458,15 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/digital_rx_chain.v">
<FileInfo SFType="SVerilog">
<File Path="$PSRCDIR/sources_1/hdl/digital_rx_chain.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/ethernet_top.v">
<FileInfo SFType="SVerilog">
<File Path="$PSRCDIR/sources_1/hdl/ethernet_top.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -486,36 +486,28 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/timing_engine.v">
<FileInfo SFType="SVerilog">
<File Path="$PSRCDIR/sources_1/hdl/timing_engine.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/util_reg.v">
<FileInfo SFType="SVerilog">
<File Path="$PSRCDIR/sources_1/hdl/util_reg.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/top.v">
<FileInfo SFType="SVerilog">
<File Path="$PSRCDIR/sources_1/hdl/top.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/waveform_gen.v">
<FileInfo SFType="SVerilog">
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/clock_converter/clock_converter.xci">
<File Path="$PSRCDIR/sources_1/ip/width_converter/width_converter.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -531,7 +523,15 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/width_converter/width_converter.xci">
<File Path="$PSRCDIR/sources_1/ip/clock_converter/clock_converter.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/waveform_gen.sv">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>