renamed system verilog files to have .sv extensions

2025-11-12 21:33:16 -06:00
parent d9a14af015
commit 5923ec0831
7 changed files with 21 additions and 21 deletions
--- a/radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.sv
--- a/radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.sv
--- a/radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.sv
--- a/radar_alinx_kintex.srcs/sources_1/hdl/top.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/top.sv
@@ -948,7 +948,7 @@ module top #
    wire [127:0] iq_out;
    wire iq_out_valid;

-    gen_ofdm dut (
+    gen_ofdm waveform_gen_i (
        .clk(jesd_core_clk),    
        .reset(1'b0),

--- a/radar_alinx_kintex.srcs/sources_1/hdl/util_reg.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/util_reg.sv
--- a/radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.sv