starting to look at waveform generator, just in python right now
This commit is contained in:
234
python/waveform_generator/wf_ofdm.py
Normal file
234
python/waveform_generator/wf_ofdm.py
Normal file
@@ -0,0 +1,234 @@
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import numpy as np
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# get one chip of a multi-chip OFDM waveform
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def get_chip(
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baseband,
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start_phase,
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f_samp,
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N_samp_chip,
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N_pulse,
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n_tx,
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n_pulse,
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n_sub_cpi,
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):
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# pylint: disable-msg=too-many-arguments
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# TODO: @Charlie, remove disable and fix
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# unused args
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s_p = np.sum(
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[
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start_phase[n_tx, n_sub_cpi, nn % N_pulse]
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for nn in range(N_pulse * n_sub_cpi + n_pulse)
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]
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)
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phase = (
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s_p + baseband[n_tx, n_sub_cpi, n_pulse] * np.arange(N_samp_chip) / f_samp
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)
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x = np.exp(2 * np.pi * 1j * phase)
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return x, phase
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# synthesize the transmit waveform in intermediate frequency sample space
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def get_waveform(baseband, start_phase, N_tx, N_sub_cpi, N_f_pulse, N_samp_chip, N_samp, f_samp):
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pulse = np.zeros((N_tx, N_sub_cpi, N_samp), dtype=complex)
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phase = np.zeros((N_tx, N_sub_cpi, N_samp))
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for n_tx in range(N_tx):
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for n_sub_cpi in range(N_sub_cpi):
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for n_f_pulse in range(N_f_pulse):
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(
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pulse[
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n_tx,
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n_sub_cpi,
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n_f_pulse * N_samp_chip: (
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N_samp_chip + n_f_pulse * N_samp_chip
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),
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],
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phase[
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n_tx,
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n_sub_cpi,
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n_f_pulse * N_samp_chip: (
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N_samp_chip + n_f_pulse * N_samp_chip
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),
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],
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) = get_chip(baseband, start_phase, f_samp, N_samp_chip, N_f_pulse, n_tx, n_f_pulse, n_sub_cpi)
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return pulse, phase
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def get_pulse_params(n_tx, n_rx, f_samp, n_samp_chip, n_f, n_f_pulse, n_sub_cpi, n_pol, perm):
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f_chip = 5859375.0
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f_c = 16300000255.999992
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k_rgft = 256
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b = 23437500.0
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t_chip = 1 / f_chip
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n_tx_n_pol = n_tx * n_pol
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# frequencies with respect to baseband
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baseband = f_chip * (perm - (n_f - 1) / 2)
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start_phase = baseband * t_chip
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f_sa = f_c + baseband
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chip_samples = int(np.ceil(k_rgft * f_chip / f_samp))
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chip_center_dmux = np.zeros((n_sub_cpi, n_rx, n_tx_n_pol, n_f_pulse), dtype=int)
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chip_lower_dmux = np.zeros((n_sub_cpi, n_rx, n_tx_n_pol, n_f_pulse), dtype=int)
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chip_upper_dmux = np.zeros((n_sub_cpi, n_rx, n_tx_n_pol, n_f_pulse), dtype=int)
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time_shift_dmux = np.zeros((n_sub_cpi, n_rx, n_tx_n_pol, n_f_pulse))
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f_sa_dmux = np.zeros((n_sub_cpi, n_rx, n_tx_n_pol, n_f_pulse))
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for n_sub_cpi_ind in range(n_sub_cpi):
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for n_rx_ind in range(n_rx):
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for n_tx_ind in range(n_tx_n_pol):
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for n_f_pulse_ind in range(n_f_pulse):
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time_shift_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = (
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n_f_pulse_ind * n_samp_chip + n_samp_chip / 2
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)
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chip_center_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = int(
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np.round(
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k_rgft
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* (baseband[n_tx_ind, n_sub_cpi_ind, n_f_pulse_ind] + b / 2)
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/ f_samp
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)
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)
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chip_lower_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = int(
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np.round(
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chip_center_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind]
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- chip_samples / 2
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)
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)
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chip_upper_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = (
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chip_lower_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] + chip_samples
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)
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f_sa_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = f_sa[
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n_tx_ind, n_sub_cpi_ind, n_f_pulse_ind
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]
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return
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def wg_ofdm():
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# wp = inputs.wp.proto # just to make code easier to read
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n_f = 4
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n_f_pulse = 4
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do_random = False
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do_agile = False
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n_sub_cpi = 1
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n_tx = 1
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n_rx = 2
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n_pol = 2
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n_samp = 32
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n_samp_chip = 8
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f_samp = 46875000.0
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tx_sample_rate_multiplier = 16
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n_gen_pulses = 1
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rng = np.random.default_rng(seed=42)
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perm_list = []
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sequence = np.arange(n_f)
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unique_sub_cpi = n_gen_pulses // n_sub_cpi
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for n_p in range(unique_sub_cpi):
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if do_random and (do_agile or n_p == 0):
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# if we are here, we are doing random pulses and
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# 1. it is pulse zero so we set the permutation for all of
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# the pulses
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# or
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# 2. we are agile and we set a new permutation for every pulse
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sequence = rng.permutation(n_f)
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elif n_p == 0:
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# if we are here, we are not random, so set the sequence equal
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# to a range, which will give an LFM waveform
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sequence = np.arange(n_f)
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if n_pol == 1:
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perm = np.reshape(
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sequence,
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(n_tx, n_sub_cpi, n_f_pulse),
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)
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elif n_pol == 2:
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perm = np.zeros(
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(
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n_pol * n_tx,
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n_sub_cpi,
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n_f_pulse,
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),
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dtype=int,
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)
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for n_tx_ind in range(n_tx):
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perm[n_tx_ind, :, :] = np.reshape(
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sequence[n_f * n_tx_ind: n_f * (n_tx_ind + 1)],
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(n_sub_cpi, n_f_pulse),
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)
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if n_tx_ind == 0:
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perm[n_tx + n_tx_ind, :, :] = np.reshape(
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sequence[n_f * (n_tx_ind + 1) - 1:: -1],
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(n_sub_cpi, n_f_pulse),
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)
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else:
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perm[n_tx + n_tx_ind, :, :] = np.reshape(
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sequence[n_f * (n_tx_ind + 1) - 1: n_f * n_tx_ind - 1: -1],
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(n_sub_cpi, n_f_pulse),
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)
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# fill the permutation we just generated in to a list
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perm_list.append(perm)
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# generate a set of pulse parameters for every element of our list
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perm_list_full = []
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# at this point, we need to create pulse parameters for the full number of
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# pulses in the CPI, even though the waveform generator will only generate
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# a subset of those.
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# so N_pulses defined above is the number of pulses to generate
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# wp.N_pulses is the total number of pulses in a CPI.
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# note that here, N_pulses = wp.N_gen_pulses is the number of pulses
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# we use to size the output buffer.
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# Additional note, in the tactical system, wp.N_gen_pulses must always
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# be equal to wp.N_pulses, these two only differ in testing.
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for n_p in range(unique_sub_cpi):
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perm_list_full.append(perm_list[n_p % unique_sub_cpi])
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# pp_list = PulseParamsList(
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# pulse_params=[get_pulse_params(wp=wp, perm=p) for p in perm_list_full]
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# )
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[get_pulse_params(n_tx, n_rx, f_samp, n_samp_chip, n_f, n_f_pulse, n_sub_cpi, n_pol, p) for p in perm_list_full]
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subpulses = np.ndarray(
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shape=(
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unique_sub_cpi,
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n_tx * n_pol,
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n_sub_cpi,
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n_samp * tx_sample_rate_multiplier,
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2, # I/Q
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),
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dtype=np.uint16,
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)
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amplitude_quant = 2 ** (16 - 1) - 1
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zero_quant = 0
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# This generates transmit waveforms for the whole CPI
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for n_cpi in range(unique_sub_cpi):
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pulse, _phase = get_waveform(
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np.array(
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pp_list.pulse_params[n_cpi].baseband.elements, dtype=np.double
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).reshape(tuple(pp_list.pulse_params[n_cpi].baseband.dimensions)),
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np.array(
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pp_list.pulse_params[n_cpi].start_phase.elements, dtype=np.double
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).reshape(tuple(pp_list.pulse_params[n_cpi].start_phase.dimensions)),
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n_tx * n_pol,
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n_sub_cpi,
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n_f_pulse,
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n_samp_chip * tx_sample_rate_multiplier,
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n_samp * tx_sample_rate_multiplier,
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f_samp * tx_sample_rate_multiplier,
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)
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subpulses[n_cpi, ..., 0] = np.round(
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(amplitude_quant * np.real(pulse) + zero_quant).astype(np.uint16)
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)
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subpulses[n_cpi, ..., 1] = np.round(
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(amplitude_quant * np.imag(pulse) + zero_quant).astype(np.uint16)
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)
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return
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if __name__ == '__main__':
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wg_ofdm()
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@@ -283,11 +283,11 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
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#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
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# Works with the board at my house
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set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
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set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
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#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
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#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
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# Works with the board Chris has (broken USB UART)
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#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
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#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
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set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
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set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
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set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
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set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
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Binary file not shown.
@@ -13,12 +13,12 @@
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<stringAttribute key="com.xilinx.sdk.tcf.debug.uidebug.type" value="STANDALONE_DEBUG"/>
|
||||
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uienable.crosstrigger" value="false"/>
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<stringAttribute key="com.xilinx.sdk.tcf.debug.uifpga.device" value="Auto Detect"/>
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<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.bit.file" value=""/>
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<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.bit.file" value="/home/bkiedinger/projects/castelion/radar_alinx_kintex/radar_alinx_kintex.runs/impl_1/download.bit"/>
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<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.init.tcl" value=""/>
|
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<booleanAttribute key="com.xilinx.sdk.tcf.debug.uipl.powerup" value="false"/>
|
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<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{"microblaze_0":{"xilinx.tcf.application":"Debug/bootloader.elf","xilinx.tcf.datafiles":"","xilinx.tcf.no_download":false,"xilinx.tcf.profile_enabled":false,"xilinx.tcf.profile_frequency":"10000","xilinx.tcf.profile_non_int_frequency":"150000000","xilinx.tcf.profile_non_int_high_addr":"","xilinx.tcf.profile_non_int_low_addr":"","xilinx.tcf.profile_non_int_use_count_instr":false,"xilinx.tcf.profile_non_int_use_cumulate":false,"xilinx.tcf.profile_non_intrusive_support":false,"xilinx.tcf.profile_store_address":"0x0","xilinx.tcf.profile_use_intrusive":false,"xilinx.tcf.project":"bootloader","xilinx.tcf.relocate":false,"xilinx.tcf.relocate_addr":"","xilinx.tcf.reset":false,"xilinx.tcf.stop_at_entry":false}}"/>
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<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{"microblaze_0":{"xilinx.tcf.application":"Debug/bootloader.elf","xilinx.tcf.datafiles":"","xilinx.tcf.no_download":false,"xilinx.tcf.profile_enabled":false,"xilinx.tcf.profile_frequency":"10000","xilinx.tcf.profile_non_int_frequency":"125000000","xilinx.tcf.profile_non_int_high_addr":"","xilinx.tcf.profile_non_int_low_addr":"","xilinx.tcf.profile_non_int_use_count_instr":false,"xilinx.tcf.profile_non_int_use_cumulate":false,"xilinx.tcf.profile_non_intrusive_support":false,"xilinx.tcf.profile_store_address":"0x0","xilinx.tcf.profile_use_intrusive":false,"xilinx.tcf.project":"bootloader","xilinx.tcf.relocate":false,"xilinx.tcf.relocate_addr":"","xilinx.tcf.reset":false,"xilinx.tcf.stop_at_entry":false}}"/>
|
||||
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.selection" value="microblaze_0"/>
|
||||
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="false"/>
|
||||
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="true"/>
|
||||
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproject.name" value="bootloader"/>
|
||||
<stringAttribute key="com.xilinx.sdk.tcf.debug.uips.device" value="Auto Detect"/>
|
||||
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uips7.init" value="false"/>
|
||||
@@ -26,7 +26,7 @@
|
||||
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.apu" value="false"/>
|
||||
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.lock.step" value="false"/>
|
||||
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.rpu" value="false"/>
|
||||
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.system" value="false"/>
|
||||
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.system" value="true"/>
|
||||
<stringAttribute key="com.xilinx.sdk.tcf.debug.uitarget.peer" value="Local"/>
|
||||
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.active.build.config" value="Debug"/>
|
||||
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.application.type" value=""/>
|
||||
|
||||
@@ -165,7 +165,7 @@ int main()
|
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uint8_t ret;
|
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|
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#ifdef VERBOSE
|
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print ("\r\nSREC SPI Bootloader\r\n");
|
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xil_printf ("\r\nSREC SPI Bootloader\r\n");
|
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#endif
|
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|
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sleep(3);
|
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@@ -183,7 +183,7 @@ int main()
|
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*/
|
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Status = XSpi_Initialize(&Spi, SPI_DEVICE_ID);
|
||||
if(Status != XST_SUCCESS) {
|
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print("init fail");
|
||||
xil_printf("init fail");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
@@ -195,7 +195,7 @@ int main()
|
||||
Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION |
|
||||
XSP_MANUAL_SSELECT_OPTION);
|
||||
if(Status != XST_SUCCESS) {
|
||||
print("options fail");
|
||||
xil_printf("options fail");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
@@ -205,7 +205,7 @@ int main()
|
||||
*/
|
||||
Status = XSpi_SetSlaveSelect(&Spi, SPI_SELECT);
|
||||
if(Status != XST_SUCCESS) {
|
||||
print("slave select fail");
|
||||
xil_printf("slave select fail");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
@@ -219,36 +219,36 @@ int main()
|
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init_stdout();
|
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sleep(1);
|
||||
|
||||
print ("Read Flash ID");
|
||||
xil_printf ("Read Flash ID");
|
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Status = FlashReadID( );
|
||||
if(Status != XST_SUCCESS) {
|
||||
print("flash read id fail");
|
||||
xil_printf("flash read id fail");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
print ("Read Flash ID");
|
||||
xil_printf ("Read Flash ID");
|
||||
Status = FlashReadID( );
|
||||
if(Status != XST_SUCCESS) {
|
||||
print("flash read id fail");
|
||||
xil_printf("flash read id fail");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
print ("Read Flash ID");
|
||||
xil_printf ("Read Flash ID");
|
||||
Status = FlashReadID( );
|
||||
if(Status != XST_SUCCESS) {
|
||||
print("flash read id fail");
|
||||
xil_printf("flash read id fail");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
|
||||
#ifdef VERBOSE
|
||||
print ("Loading SREC image from flash @ address: ");
|
||||
xil_printf ("Loading SREC image from flash @ address: ");
|
||||
putnum (FLASH_IMAGE_BASEADDR);
|
||||
print ("\r\n");
|
||||
xil_printf ("\r\n");
|
||||
#endif
|
||||
|
||||
sleep(1);
|
||||
print ("After Sleep");
|
||||
xil_printf ("After Sleep");
|
||||
|
||||
flbuf = (u32)FLASH_IMAGE_BASEADDR;
|
||||
ret = load_exec ();
|
||||
@@ -257,12 +257,12 @@ int main()
|
||||
|
||||
#ifdef VERBOSE
|
||||
if (ret > LD_SREC_LINE_ERROR) {
|
||||
print ("ERROR in SREC line: ");
|
||||
xil_printf ("ERROR in SREC line: ");
|
||||
putnum (srec_line);
|
||||
print (errors[ret]);
|
||||
xil_printf (errors[ret]);
|
||||
} else {
|
||||
print ("ERROR: ");
|
||||
print (errors[ret]);
|
||||
xil_printf ("ERROR: ");
|
||||
xil_printf (errors[ret]);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -386,9 +386,9 @@ static void display_progress (uint32_t count)
|
||||
{
|
||||
/* Send carriage return */
|
||||
outbyte (CR);
|
||||
print ("Bootloader: Processed (0x)");
|
||||
xil_printf ("Bootloader: Processed (0x)");
|
||||
putnum (count);
|
||||
print (" S-records");
|
||||
xil_printf (" S-records");
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -417,7 +417,7 @@ static uint8_t load_exec ()
|
||||
|
||||
#ifdef VERBOSE
|
||||
if (srec_line % 16 == 0) {
|
||||
// Don't print every line because it takes forever over UART
|
||||
// Don't xil_printf every line because it takes forever over UART
|
||||
display_progress (srec_line);
|
||||
}
|
||||
#endif
|
||||
@@ -449,9 +449,9 @@ static uint8_t load_exec ()
|
||||
mode = READ_WRITE_EXTRA_BYTES;
|
||||
}
|
||||
#ifdef VERBOSE
|
||||
print ("\r\nExecuting program starting at address: ");
|
||||
xil_printf ("\r\nExecuting program starting at address: ");
|
||||
putnum ((uint32_t)laddr);
|
||||
print ("\r\n");
|
||||
xil_printf ("\r\n");
|
||||
#endif
|
||||
(*laddr)();
|
||||
|
||||
|
||||
@@ -10,10 +10,15 @@
|
||||
# source /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/bootloader_system/_ide/scripts/debugger_bootloader-default.tcl
|
||||
#
|
||||
connect -url tcp:127.0.0.1:3121
|
||||
targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && level==0 && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-13822093-0"}
|
||||
fpga -file /home/bkiedinger/projects/castelion/radar_alinx_kintex/radar_alinx_kintex.runs/impl_1/download.bit
|
||||
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
|
||||
loadhw -hw /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/hw/top.xsa -regs
|
||||
configparams mdm-detect-bscan-mask 2
|
||||
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
|
||||
rst -system
|
||||
after 3000
|
||||
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
|
||||
dow /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/bootloader/Debug/bootloader.elf
|
||||
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
|
||||
con
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="ASCII"?>
|
||||
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="b81ac1744f29e93881cfaa8e8b019a98">
|
||||
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="31c4a066f121f9dfdf4b2a6e46d178c9">
|
||||
<configuration name="Debug" id="xilinx.gnu.mb.exe.debug.245787499">
|
||||
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
|
||||
@@ -525,23 +525,23 @@ void setup_data_converter() {
|
||||
#ifndef IBERT_TESTING
|
||||
|
||||
// Update FPGA TX Transceiver settings
|
||||
// set_lane_cal(0, 0, 0, 11);
|
||||
// set_lane_cal(1, 10, 5, 11);
|
||||
// set_lane_cal(2, 5, 0, 11);
|
||||
// set_lane_cal(3, 0, 0, 11);
|
||||
// set_lane_cal(4, 0, 0, 11);
|
||||
// set_lane_cal(5, 0, 0, 11);
|
||||
// set_lane_cal(6, 12, 0, 11);
|
||||
// set_lane_cal(7, 0, 0, 11);
|
||||
set_lane_cal(0, 0, 0, 11);
|
||||
set_lane_cal(1, 10, 5, 11);
|
||||
set_lane_cal(2, 5, 0, 11);
|
||||
set_lane_cal(3, 0, 0, 11);
|
||||
set_lane_cal(4, 0, 0, 11);
|
||||
set_lane_cal(5, 0, 0, 11);
|
||||
set_lane_cal(6, 12, 0, 11);
|
||||
set_lane_cal(7, 0, 0, 11);
|
||||
|
||||
set_lane_cal(0, 9, 0, 7);
|
||||
set_lane_cal(1, 9, 0, 7);
|
||||
set_lane_cal(2, 9, 0, 7);
|
||||
set_lane_cal(3, 9, 0, 7);
|
||||
set_lane_cal(4, 9, 0, 7);
|
||||
set_lane_cal(5, 9, 0, 7);
|
||||
set_lane_cal(6, 9, 0, 7);
|
||||
set_lane_cal(7, 9, 0, 7);
|
||||
// set_lane_cal(0, 9, 0, 7);
|
||||
// set_lane_cal(1, 9, 0, 7);
|
||||
// set_lane_cal(2, 9, 0, 7);
|
||||
// set_lane_cal(3, 9, 0, 7);
|
||||
// set_lane_cal(4, 9, 0, 7);
|
||||
// set_lane_cal(5, 9, 0, 7);
|
||||
// set_lane_cal(6, 9, 0, 7);
|
||||
// set_lane_cal(7, 9, 0, 7);
|
||||
|
||||
vTaskDelay(100);
|
||||
int subclass = jtx_param[uc][0].jesd_subclass;
|
||||
|
||||
@@ -496,8 +496,8 @@
|
||||
#define PLATFORM_MB
|
||||
|
||||
/******************************************************************/
|
||||
#define STDIN_BASEADDRESS 0x40000000
|
||||
#define STDOUT_BASEADDRESS 0x40000000
|
||||
#define STDIN_BASEADDRESS 0x41400000
|
||||
#define STDOUT_BASEADDRESS 0x41400000
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -6,8 +6,8 @@ BEGIN OS
|
||||
PARAMETER OS_NAME = freertos10_xilinx
|
||||
PARAMETER OS_VER = 1.12
|
||||
PARAMETER PROC_INSTANCE = microblaze_0
|
||||
PARAMETER stdin = axi_uartlite_0
|
||||
PARAMETER stdout = axi_uartlite_0
|
||||
PARAMETER stdin = mdm_1
|
||||
PARAMETER stdout = mdm_1
|
||||
PARAMETER total_heap_size = 2097152
|
||||
END
|
||||
|
||||
|
||||
@@ -1 +1 @@
|
||||
{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"4c4ac3edab33e057a6d0ea5f5fe6bbb4","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"total_heap_size":"2097152","libOptionNames":["total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
|
||||
{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"b936724655c64fcfe17fbda77eb413eb","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"stdin":"mdm_1","stdout":"mdm_1","total_heap_size":"2097152","libOptionNames":["stdin","stdout","total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
|
||||
|
||||
@@ -210,3 +210,29 @@ bsp reload
|
||||
catch {bsp regenerate}
|
||||
platform generate -domains freertos10_xilinx_microblaze_0
|
||||
platform active {top}
|
||||
platform active {top}
|
||||
bsp reload
|
||||
bsp config stdin "mdm_1"
|
||||
bsp config stdout "mdm_1"
|
||||
bsp write
|
||||
bsp reload
|
||||
catch {bsp regenerate}
|
||||
bsp write
|
||||
platform generate
|
||||
platform active {top}
|
||||
platform generate -domains
|
||||
bsp reload
|
||||
bsp config stdin "axi_uartlite_0"
|
||||
bsp config stdout "axi_uartlite_0"
|
||||
bsp write
|
||||
bsp reload
|
||||
catch {bsp regenerate}
|
||||
platform generate -domains freertos10_xilinx_microblaze_0
|
||||
platform active {top}
|
||||
bsp reload
|
||||
bsp config stdin "mdm_1"
|
||||
bsp config stdout "mdm_1"
|
||||
bsp write
|
||||
bsp reload
|
||||
catch {bsp regenerate}
|
||||
platform generate -domains freertos10_xilinx_microblaze_0
|
||||
|
||||
Reference in New Issue
Block a user