bkiedinger/castelion_radar_alinx_kintex
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starting to look at waveform generator, just in python right now

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bkiedinger@gmail.com
2025-09-10 21:43:06 -05:00
parent 3648531294
commit d1ccfb8357
14 changed files with 317 additions and 52 deletions
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8
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
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@@ -283,11 +283,11 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
# Works with the board at my house
set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
# Works with the board Chris has (broken USB UART)
#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]

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radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
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