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starting to look at waveform generator, just in python right now

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bkiedinger@gmail.com
2025-09-10 21:43:06 -05:00
parent 3648531294
commit d1ccfb8357
14 changed files with 317 additions and 52 deletions
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8
vitis/bootloader/_ide/launch/Debugger_bootloader-Default.launch
View File

@@ -13,12 +13,12 @@
<stringAttribute key="com.xilinx.sdk.tcf.debug.uidebug.type" value="STANDALONE_DEBUG"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uienable.crosstrigger" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uifpga.device" value="Auto Detect"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.bit.file" value=""/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.bit.file" value="/home/bkiedinger/projects/castelion/radar_alinx_kintex/radar_alinx_kintex.runs/impl_1/download.bit"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.init.tcl" value=""/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uipl.powerup" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{&quot;microblaze_0&quot;:{&quot;xilinx.tcf.application&quot;:&quot;Debug/bootloader.elf&quot;,&quot;xilinx.tcf.datafiles&quot;:&quot;&quot;,&quot;xilinx.tcf.no_download&quot;:false,&quot;xilinx.tcf.profile_enabled&quot;:false,&quot;xilinx.tcf.profile_frequency&quot;:&quot;10000&quot;,&quot;xilinx.tcf.profile_non_int_frequency&quot;:&quot;150000000&quot;,&quot;xilinx.tcf.profile_non_int_high_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_low_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_use_count_instr&quot;:false,&quot;xilinx.tcf.profile_non_int_use_cumulate&quot;:false,&quot;xilinx.tcf.profile_non_intrusive_support&quot;:false,&quot;xilinx.tcf.profile_store_address&quot;:&quot;0x0&quot;,&quot;xilinx.tcf.profile_use_intrusive&quot;:false,&quot;xilinx.tcf.project&quot;:&quot;bootloader&quot;,&quot;xilinx.tcf.relocate&quot;:false,&quot;xilinx.tcf.relocate_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.reset&quot;:false,&quot;xilinx.tcf.stop_at_entry&quot;:false}}"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{&quot;microblaze_0&quot;:{&quot;xilinx.tcf.application&quot;:&quot;Debug/bootloader.elf&quot;,&quot;xilinx.tcf.datafiles&quot;:&quot;&quot;,&quot;xilinx.tcf.no_download&quot;:false,&quot;xilinx.tcf.profile_enabled&quot;:false,&quot;xilinx.tcf.profile_frequency&quot;:&quot;10000&quot;,&quot;xilinx.tcf.profile_non_int_frequency&quot;:&quot;125000000&quot;,&quot;xilinx.tcf.profile_non_int_high_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_low_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_use_count_instr&quot;:false,&quot;xilinx.tcf.profile_non_int_use_cumulate&quot;:false,&quot;xilinx.tcf.profile_non_intrusive_support&quot;:false,&quot;xilinx.tcf.profile_store_address&quot;:&quot;0x0&quot;,&quot;xilinx.tcf.profile_use_intrusive&quot;:false,&quot;xilinx.tcf.project&quot;:&quot;bootloader&quot;,&quot;xilinx.tcf.relocate&quot;:false,&quot;xilinx.tcf.relocate_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.reset&quot;:false,&quot;xilinx.tcf.stop_at_entry&quot;:false}}"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.selection" value="microblaze_0"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="true"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproject.name" value="bootloader"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uips.device" value="Auto Detect"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uips7.init" value="false"/>
@@ -26,7 +26,7 @@
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.apu" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.lock.step" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.rpu" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.system" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.system" value="true"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uitarget.peer" value="Local"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.active.build.config" value="Debug"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.application.type" value=""/>

44
vitis/bootloader/src/bootloader.c
View File

@@ -165,7 +165,7 @@ int main()
uint8_t ret;
#ifdef VERBOSE
print ("\r\nSREC SPI Bootloader\r\n");
xil_printf ("\r\nSREC SPI Bootloader\r\n");
#endif
sleep(3);
@@ -183,7 +183,7 @@ int main()
*/
Status = XSpi_Initialize(&Spi, SPI_DEVICE_ID);
if(Status != XST_SUCCESS) {
print("init fail");
xil_printf("init fail");
return XST_FAILURE;
}
@@ -195,7 +195,7 @@ int main()
Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION |
XSP_MANUAL_SSELECT_OPTION);
if(Status != XST_SUCCESS) {
print("options fail");
xil_printf("options fail");
return XST_FAILURE;
}
@@ -205,7 +205,7 @@ int main()
*/
Status = XSpi_SetSlaveSelect(&Spi, SPI_SELECT);
if(Status != XST_SUCCESS) {
print("slave select fail");
xil_printf("slave select fail");
return XST_FAILURE;
}
@@ -219,36 +219,36 @@ int main()
init_stdout();
sleep(1);
print ("Read Flash ID");
xil_printf ("Read Flash ID");
Status = FlashReadID( );
if(Status != XST_SUCCESS) {
print("flash read id fail");
xil_printf("flash read id fail");
return XST_FAILURE;
}
print ("Read Flash ID");
xil_printf ("Read Flash ID");
Status = FlashReadID( );
if(Status != XST_SUCCESS) {
print("flash read id fail");
xil_printf("flash read id fail");
return XST_FAILURE;
}
print ("Read Flash ID");
xil_printf ("Read Flash ID");
Status = FlashReadID( );
if(Status != XST_SUCCESS) {
print("flash read id fail");
xil_printf("flash read id fail");
return XST_FAILURE;
}
#ifdef VERBOSE
print ("Loading SREC image from flash @ address: ");
xil_printf ("Loading SREC image from flash @ address: ");
putnum (FLASH_IMAGE_BASEADDR);
print ("\r\n");
xil_printf ("\r\n");
#endif
sleep(1);
print ("After Sleep");
xil_printf ("After Sleep");
flbuf = (u32)FLASH_IMAGE_BASEADDR;
ret = load_exec ();
@@ -257,12 +257,12 @@ int main()
#ifdef VERBOSE
if (ret > LD_SREC_LINE_ERROR) {
print ("ERROR in SREC line: ");
xil_printf ("ERROR in SREC line: ");
putnum (srec_line);
print (errors[ret]);
xil_printf (errors[ret]);
} else {
print ("ERROR: ");
print (errors[ret]);
xil_printf ("ERROR: ");
xil_printf (errors[ret]);
}
#endif
@@ -386,9 +386,9 @@ static void display_progress (uint32_t count)
{
/* Send carriage return */
outbyte (CR);
print ("Bootloader: Processed (0x)");
xil_printf ("Bootloader: Processed (0x)");
putnum (count);
print (" S-records");
xil_printf (" S-records");
}
#endif
@@ -417,7 +417,7 @@ static uint8_t load_exec ()
#ifdef VERBOSE
if (srec_line % 16 == 0) {
// Don't print every line because it takes forever over UART
// Don't xil_printf every line because it takes forever over UART
display_progress (srec_line);
}
#endif
@@ -449,9 +449,9 @@ static uint8_t load_exec ()
mode = READ_WRITE_EXTRA_BYTES;
}
#ifdef VERBOSE
print ("\r\nExecuting program starting at address: ");
xil_printf ("\r\nExecuting program starting at address: ");
putnum ((uint32_t)laddr);
print ("\r\n");
xil_printf ("\r\n");
#endif
(*laddr)();

5
vitis/bootloader_system/_ide/scripts/debugger_bootloader-default.tcl
View File

@@ -10,10 +10,15 @@
# source /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/bootloader_system/_ide/scripts/debugger_bootloader-default.tcl
#
connect -url tcp:127.0.0.1:3121
targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && level==0 && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-13822093-0"}
fpga -file /home/bkiedinger/projects/castelion/radar_alinx_kintex/radar_alinx_kintex.runs/impl_1/download.bit
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
loadhw -hw /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/hw/top.xsa -regs
configparams mdm-detect-bscan-mask 2
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
rst -system
after 3000
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
dow /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/bootloader/Debug/bootloader.elf
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
con

2
vitis/radar/radar.prj
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="b81ac1744f29e93881cfaa8e8b019a98">
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="31c4a066f121f9dfdf4b2a6e46d178c9">
<configuration name="Debug" id="xilinx.gnu.mb.exe.debug.245787499">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>

32
vitis/radar/src/data_converter_setup.c
View File

@@ -525,23 +525,23 @@ void setup_data_converter() {
#ifndef IBERT_TESTING
// Update FPGA TX Transceiver settings
// set_lane_cal(0, 0, 0, 11);
// set_lane_cal(1, 10, 5, 11);
// set_lane_cal(2, 5, 0, 11);
// set_lane_cal(3, 0, 0, 11);
// set_lane_cal(4, 0, 0, 11);
// set_lane_cal(5, 0, 0, 11);
// set_lane_cal(6, 12, 0, 11);
// set_lane_cal(7, 0, 0, 11);
set_lane_cal(0, 0, 0, 11);
set_lane_cal(1, 10, 5, 11);
set_lane_cal(2, 5, 0, 11);
set_lane_cal(3, 0, 0, 11);
set_lane_cal(4, 0, 0, 11);
set_lane_cal(5, 0, 0, 11);
set_lane_cal(6, 12, 0, 11);
set_lane_cal(7, 0, 0, 11);
set_lane_cal(0, 9, 0, 7);
set_lane_cal(1, 9, 0, 7);
set_lane_cal(2, 9, 0, 7);
set_lane_cal(3, 9, 0, 7);
set_lane_cal(4, 9, 0, 7);
set_lane_cal(5, 9, 0, 7);
set_lane_cal(6, 9, 0, 7);
set_lane_cal(7, 9, 0, 7);
// set_lane_cal(0, 9, 0, 7);
// set_lane_cal(1, 9, 0, 7);
// set_lane_cal(2, 9, 0, 7);
// set_lane_cal(3, 9, 0, 7);
// set_lane_cal(4, 9, 0, 7);
// set_lane_cal(5, 9, 0, 7);
// set_lane_cal(6, 9, 0, 7);
// set_lane_cal(7, 9, 0, 7);
vTaskDelay(100);
int subclass = jtx_param[uc][0].jesd_subclass;

4
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h
View File

@@ -496,8 +496,8 @@
#define PLATFORM_MB
/******************************************************************/
#define STDIN_BASEADDRESS 0x40000000
#define STDOUT_BASEADDRESS 0x40000000
#define STDIN_BASEADDRESS 0x41400000
#define STDOUT_BASEADDRESS 0x41400000
/******************************************************************/

BIN
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a
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Binary file not shown.

BIN
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a
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Binary file not shown.

4
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss
View File

@@ -6,8 +6,8 @@ BEGIN OS
PARAMETER OS_NAME = freertos10_xilinx
PARAMETER OS_VER = 1.12
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER stdin = axi_uartlite_0
PARAMETER stdout = axi_uartlite_0
PARAMETER stdin = mdm_1
PARAMETER stdout = mdm_1
PARAMETER total_heap_size = 2097152
END

2
vitis/top/platform.spr
View File

@@ -1 +1 @@
{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"4c4ac3edab33e057a6d0ea5f5fe6bbb4","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"total_heap_size":"2097152","libOptionNames":["total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"b936724655c64fcfe17fbda77eb413eb","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"stdin":"mdm_1","stdout":"mdm_1","total_heap_size":"2097152","libOptionNames":["stdin","stdout","total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}

26
vitis/top/platform.tcl
View File

@@ -210,3 +210,29 @@ bsp reload
catch {bsp regenerate}
platform generate -domains freertos10_xilinx_microblaze_0
platform active {top}
platform active {top}
bsp reload
bsp config stdin "mdm_1"
bsp config stdout "mdm_1"
bsp write
bsp reload
catch {bsp regenerate}
bsp write
platform generate
platform active {top}
platform generate -domains
bsp reload
bsp config stdin "axi_uartlite_0"
bsp config stdout "axi_uartlite_0"
bsp write
bsp reload
catch {bsp regenerate}
platform generate -domains freertos10_xilinx_microblaze_0
platform active {top}
bsp reload
bsp config stdin "mdm_1"
bsp config stdout "mdm_1"
bsp write
bsp reload
catch {bsp regenerate}
platform generate -domains freertos10_xilinx_microblaze_0