bkiedinger/castelion_radar_alinx_kintex
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decimation working

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bkiedinger@gmail.com
2025-06-11 08:36:31 -05:00
parent 316ae900ae
commit d60c55f292
31 changed files with 17172 additions and 12834 deletions
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211
radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.v
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@@ -7,6 +7,7 @@ module digital_rx_chain #
parameter CTRL_REG_ADDR = 32'h00000000,
parameter NUM_SAMPLES_REG_ADDR = 32'h00000004,
parameter START_SAMPLE_REG_ADDR = 32'h00000008,
parameter DEC_SELECT_REG_ADDR = 32'h0000000C,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 32,
@@ -34,6 +35,8 @@ module digital_rx_chain #
reg out_tvalid_r;
wire out_tlast_r;
wire out_tstart_r;
reg [63:0] out_tdata_i_r;
reg [63:0] out_tdata_q_r;
// ------------------------------
// Register Inputs for timing
@@ -45,8 +48,19 @@ reg [JESD_DATA_WIDTH-1:0] in_tdata_q_reg;
always @ (posedge clk) begin
in_tstart_reg <= start_of_pulse;
in_tvalid_reg <= in_tvalid;
in_tdata_i_reg <= in_tdata_i;
in_tdata_q_reg <= in_tdata_q;
// in_tdata_i_reg <= in_tdata_i;
// in_tdata_q_reg <= in_tdata_q;
in_tdata_i_reg[15:0] = in_tdata_i[63:48];
in_tdata_i_reg[31:16] = in_tdata_i[47:32];
in_tdata_i_reg[47:32] = in_tdata_i[31:16];
in_tdata_i_reg[63:48] = in_tdata_i[15:0];
in_tdata_q_reg[15:0] = in_tdata_q[63:48];
in_tdata_q_reg[31:16] = in_tdata_q[47:32];
in_tdata_q_reg[47:32] = in_tdata_q[31:16];
in_tdata_q_reg[63:48] = in_tdata_q[15:0];
end
@@ -105,6 +119,7 @@ wire reset;
reg [31:0] reg_ctrl;
reg [15:0] reg_num_samples;
reg [27:0] reg_start_sample;
reg [3:0] reg_dec_select;
always @ (posedge ctrl_if.clk) begin
if (~ctrl_if.resetn) begin
@@ -130,6 +145,14 @@ always @ (posedge ctrl_if.clk) begin
end
end
always @ (posedge ctrl_if.clk) begin
if (~ctrl_if.resetn) begin
reg_dec_select <= 0;
end else if (wren && waddr[11:0] == DEC_SELECT_REG_ADDR) begin
reg_dec_select <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (rden) begin
if ( raddr[11:0] == CTRL_REG_ADDR )
@@ -138,6 +161,8 @@ always @ (posedge ctrl_if.clk) begin
rdata <= reg_num_samples;
if ( raddr[11:0] == START_SAMPLE_REG_ADDR )
rdata <= reg_start_sample;
if ( raddr[11:0] == DEC_SELECT_REG_ADDR )
rdata <= reg_dec_select;
end
end
@@ -167,6 +192,7 @@ reg pulse_active;
reg pulse_active_q;
reg pulse_active_fed;
reg pulse_active_fed_q;
reg pulse_active_fed_stretch;
// Delay event pulse by start sample
reg [27:0] start_sample_cnt;
@@ -200,6 +226,9 @@ always @ (posedge clk) begin
end
end
// Reset for filters after pulse
assign pulse_active_fed_stretch = pulse_active_fed || pulse_active_fed_q;
always @ (posedge clk) begin
if (reset == 1'b1) begin
sample_cnt <= 0;
@@ -231,7 +260,157 @@ end
assign out_tlast_r = ((sample_cnt == reg_num_samples-1) && out_tvalid_r) ? 1'b1 : 1'b0;
assign out_tstart_r = ((sample_cnt == 0) && out_tvalid_r) ? 1'b1 : 1'b0;
assign out_tvalid_r = in_tvalid_reg && (pulse_active || delay_active_fed);
//assign out_tvalid_r = in_tvalid_reg && (pulse_active || delay_active_fed);
// ------------------------------
// Decimation
// ------------------------------
wire dec_by_2_tvalid_i;
wire dec_by_2_tvalid_q;
wire [95:0] dec_by_2_tdata_i;
wire [95:0] dec_by_2_tdata_q;
wire [63:0] dec_by_2_tdata_i_slice;
wire [63:0] dec_by_2_tdata_q_slice;
wire dec_by_4_tvalid_i;
wire dec_by_4_tvalid_q;
wire [95:0] dec_by_4_tdata_i;
wire [95:0] dec_by_4_tdata_q;
wire [63:0] dec_by_4_tdata_i_slice;
wire [63:0] dec_by_4_tdata_q_slice;
wire dec_by_8_tvalid_i;
wire dec_by_8_tvalid_q;
wire [95:0] dec_by_8_tdata_i;
wire [95:0] dec_by_8_tdata_q;
wire [63:0] dec_by_8_tdata_i_slice;
wire [63:0] dec_by_8_tdata_q_slice;
wire dec_by_16_tvalid_i;
wire dec_by_16_tvalid_q;
wire [95:0] dec_by_16_tdata_i;
wire [95:0] dec_by_16_tdata_q;
wire [63:0] dec_by_16_tdata_i_slice;
wire [63:0] dec_by_16_tdata_q_slice;
wire dec_in_valid;
assign dec_in_valid = in_tvalid_reg && (pulse_active || delay_active_fed);
decimation_bd decimation_bd_i
(.rstn(~pulse_active_fed_stretch),
.clk(clk),
.in_i_tdata(in_tdata_i_reg),
.in_i_tready(),
.in_i_tvalid(dec_in_valid),
.dec_by_2_tdata(dec_by_2_tdata_i),
.dec_by_2_tvalid(dec_by_2_tvalid_i),
.dec_by_2_tready(1'b1),
.dec_by_4_tdata(dec_by_4_tdata_i),
.dec_by_4_tvalid(dec_by_4_tvalid_i),
.dec_by_4_tready(1'b1),
.dec_by_8_tdata(dec_by_8_tdata_i),
.dec_by_8_tvalid(dec_by_8_tvalid_i),
.dec_by_8_tready(1'b1),
.dec_by_16_tdata(dec_by_16_tdata_i),
.dec_by_16_tvalid(dec_by_16_tvalid_i),
.dec_by_16_tready(1'b1)
);
decimation_bd decimation_bd_q
(.rstn(~pulse_active_fed_stretch),
.clk(clk),
.in_i_tdata(in_tdata_q_reg),
.in_i_tready(),
.in_i_tvalid(dec_in_valid),
.dec_by_2_tdata(dec_by_2_tdata_q),
.dec_by_2_tvalid(dec_by_2_tvalid_q),
.dec_by_2_tready(1'b1),
.dec_by_4_tdata(dec_by_4_tdata_q),
.dec_by_4_tvalid(dec_by_4_tvalid_q),
.dec_by_4_tready(1'b1),
.dec_by_8_tdata(dec_by_8_tdata_q),
.dec_by_8_tvalid(dec_by_8_tvalid_q),
.dec_by_8_tready(1'b1),
.dec_by_16_tdata(dec_by_16_tdata_q),
.dec_by_16_tvalid(dec_by_16_tvalid_q),
.dec_by_16_tready(1'b1)
);
assign dec_by_2_tdata_i_slice[15:0] = dec_by_2_tdata_i[15:0];
assign dec_by_2_tdata_i_slice[31:16] = dec_by_2_tdata_i[39:24];
assign dec_by_2_tdata_i_slice[47:32] = dec_by_2_tdata_i[63:48];
assign dec_by_2_tdata_i_slice[63:48] = dec_by_2_tdata_i[87:72];
assign dec_by_2_tdata_q_slice[15:0] = dec_by_2_tdata_q[15:0];
assign dec_by_2_tdata_q_slice[31:16] = dec_by_2_tdata_q[39:24];
assign dec_by_2_tdata_q_slice[47:32] = dec_by_2_tdata_q[63:48];
assign dec_by_2_tdata_q_slice[63:48] = dec_by_2_tdata_q[87:72];
assign dec_by_4_tdata_i_slice[15:0] = dec_by_4_tdata_i[15:0];
assign dec_by_4_tdata_i_slice[31:16] = dec_by_4_tdata_i[39:24];
assign dec_by_4_tdata_i_slice[47:32] = dec_by_4_tdata_i[63:48];
assign dec_by_4_tdata_i_slice[63:48] = dec_by_4_tdata_i[87:72];
assign dec_by_4_tdata_q_slice[15:0] = dec_by_4_tdata_q[15:0];
assign dec_by_4_tdata_q_slice[31:16] = dec_by_4_tdata_q[39:24];
assign dec_by_4_tdata_q_slice[47:32] = dec_by_4_tdata_q[63:48];
assign dec_by_4_tdata_q_slice[63:48] = dec_by_4_tdata_q[87:72];
assign dec_by_8_tdata_i_slice[15:0] = dec_by_8_tdata_i[15:0];
assign dec_by_8_tdata_i_slice[31:16] = dec_by_8_tdata_i[39:24];
assign dec_by_8_tdata_i_slice[47:32] = dec_by_8_tdata_i[63:48];
assign dec_by_8_tdata_i_slice[63:48] = dec_by_8_tdata_i[87:72];
assign dec_by_8_tdata_q_slice[15:0] = dec_by_8_tdata_q[15:0];
assign dec_by_8_tdata_q_slice[31:16] = dec_by_8_tdata_q[39:24];
assign dec_by_8_tdata_q_slice[47:32] = dec_by_8_tdata_q[63:48];
assign dec_by_8_tdata_q_slice[63:48] = dec_by_8_tdata_q[87:72];
assign dec_by_16_tdata_i_slice[15:0] = dec_by_16_tdata_i[15:0];
assign dec_by_16_tdata_i_slice[31:16] = dec_by_16_tdata_i[39:24];
assign dec_by_16_tdata_i_slice[47:32] = dec_by_16_tdata_i[63:48];
assign dec_by_16_tdata_i_slice[63:48] = dec_by_16_tdata_i[87:72];
assign dec_by_16_tdata_q_slice[15:0] = dec_by_16_tdata_q[15:0];
assign dec_by_16_tdata_q_slice[31:16] = dec_by_16_tdata_q[39:24];
assign dec_by_16_tdata_q_slice[47:32] = dec_by_16_tdata_q[63:48];
assign dec_by_16_tdata_q_slice[63:48] = dec_by_16_tdata_q[87:72];
// ------------------------------
// Decimation Selection
// ------------------------------
always @ * begin
case(reg_dec_select)
4'b000 : out_tvalid_r = in_tvalid_reg && (pulse_active || delay_active_fed);
4'b001 : out_tvalid_r = dec_by_2_tvalid_i;
4'b010 : out_tvalid_r = dec_by_4_tvalid_i;
4'b011 : out_tvalid_r = dec_by_8_tvalid_i;
4'b100 : out_tvalid_r = dec_by_16_tvalid_i;
default : out_tvalid_r = 1'b0;
endcase
end
always @ * begin
case(reg_dec_select)
4'b000 : out_tdata_i_r = in_tdata_i_reg;
4'b001 : out_tdata_i_r = dec_by_2_tdata_i_slice;
4'b010 : out_tdata_i_r = dec_by_4_tdata_i_slice;
4'b011 : out_tdata_i_r = dec_by_8_tdata_i_slice;
4'b100 : out_tdata_i_r = dec_by_16_tdata_i_slice;
default : out_tdata_i_r = 1'b0;
endcase
end
always @ * begin
case(reg_dec_select)
4'b000 : out_tdata_q_r = in_tdata_q_reg;
4'b001 : out_tdata_q_r = dec_by_2_tdata_q_slice;
4'b010 : out_tdata_q_r = dec_by_4_tdata_q_slice;
4'b011 : out_tdata_q_r = dec_by_8_tdata_q_slice;
4'b100 : out_tdata_q_r = dec_by_16_tdata_q_slice;
default : out_tdata_q_r = 1'b0;
endcase
end
// ------------------------------
// Buffer
@@ -267,15 +446,25 @@ assign axis_odec_out.tvalid = out_tvalid_r && (pulse_active || delay_active_fed)
assign axis_odec_out.tlast = out_tlast_r;
assign axis_odec_out.tuser = out_tstart_r;
assign axis_odec_out.tdata[15:0] = out_tdata_i_r[15:0];
assign axis_odec_out.tdata[31:16] = out_tdata_q_r[15:0];
assign axis_odec_out.tdata[47:32] = out_tdata_i_r[31:16];
assign axis_odec_out.tdata[63:48] = out_tdata_q_r[31:16];
assign axis_odec_out.tdata[79:64] = out_tdata_i_r[47:32];
assign axis_odec_out.tdata[95:80] = out_tdata_q_r[47:32];
assign axis_odec_out.tdata[111:96] = out_tdata_i_r[63:48];
assign axis_odec_out.tdata[127:112] = out_tdata_q_r[63:48];
//assign axis_odec_out.tdata[15:0] = in_tdata_i_reg[63:48];
//assign axis_odec_out.tdata[31:16] = in_tdata_q_reg[63:48];
//assign axis_odec_out.tdata[47:32] = in_tdata_i_reg[47:32];
//assign axis_odec_out.tdata[63:48] = in_tdata_q_reg[47:32];
//assign axis_odec_out.tdata[79:64] = in_tdata_i_reg[31:16];
//assign axis_odec_out.tdata[95:80] = in_tdata_q_reg[31:16];
//assign axis_odec_out.tdata[111:96] = in_tdata_i_reg[15:0];
//assign axis_odec_out.tdata[127:112] = in_tdata_q_reg[15:0];
//204C
assign axis_odec_out.tdata[15:0] = in_tdata_i_reg[63:48];
assign axis_odec_out.tdata[31:16] = in_tdata_q_reg[63:48];
assign axis_odec_out.tdata[47:32] = in_tdata_i_reg[47:32];
assign axis_odec_out.tdata[63:48] = in_tdata_q_reg[47:32];
assign axis_odec_out.tdata[79:64] = in_tdata_i_reg[31:16];
assign axis_odec_out.tdata[95:80] = in_tdata_q_reg[31:16];
assign axis_odec_out.tdata[111:96] = in_tdata_i_reg[15:0];
assign axis_odec_out.tdata[127:112] = in_tdata_q_reg[15:0];
pulse_buffer_fifo pulse_buffer_fifo_i (
.s_axis_aresetn(~reset),