fixing pulse gen bugs

radar_alinx_kintex.srcs/sources_1/hdl/pulse_generator.v

@@ -10,7 +10,7 @@ module pulse_generator #
     input  wire                     clk,
     input  wire                     rst,
     input  wire [COUNTER_BITS-1:0]  pulse_length,
-    output wire                     start_of_pulse,
+    input  wire                     start_of_pulse,
     output wire                     pulse_out
 );
 
@@ -22,9 +22,11 @@ assign pulse_out = pulse_active;
 always @ (posedge clk) begin
     if (rst == 1'b1) begin
         pulse_cnt <= 0;
+        pulse_active <= 0;
     end else begin
         if (start_of_pulse) begin
             pulse_active <= 1;
+            pulse_cnt <= pulse_length;
         end
 
         if (pulse_active) begin
@@ -38,7 +40,6 @@ always @ (posedge clk) begin
 end
 
 
-
 endmodule
 
 

radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.sv

@@ -403,7 +403,7 @@ genvar j;
 generate
     for (j = 0; j < NUM_TIMING_PULSES; j = j + 1) begin
     
-        assign timing_pulses[j] =  timing_pulses_i | reg_pulse_start[j][28];
+        assign timing_pulses[j] =  timing_pulses_i[j] | reg_pulse_start[j][28];
     
         always @ (posedge clk) begin
             if (pri_cnt == reg_pulse_start[j][27:0]) begin
@@ -413,7 +413,7 @@ generate
             end
         end
     
-        pulse_generator (
+        pulse_generator pulse_generator_i(
             .clk(clk),
             .rst(rst),
             .pulse_length(reg_pulse_width[j]),

radar_alinx_kintex.srcs/sources_1/sim/tb_timing_engine.sv

@@ -0,0 +1,111 @@
+`timescale 1ns / 1ps
+
+import axi_vip_pkg::*;
+import axi_vip_0_pkg::*;
+
+module testbench();
+
+
+reg clk;
+reg reset;
+reg resetn;
+
+assign resetn = ~reset;
+
+localparam T = 4;
+always #(T/2) clk=~clk;
+
+axi4l_intf # (
+  .AXI_ADDR_WIDTH(32), 
+  .AXI_DATA_WIDTH(32)
+) 
+ctrl_if (
+  .clk(clk),
+  .resetn(resetn)
+);
+
+axi_vip_0_mst_t  vip_mst;
+xil_axi_resp_t     resp;
+
+axi_vip_0 axi_vip_inst (
+  .aclk(clk),                   
+  .aresetn(resetn),             
+  .m_axi_awaddr( ctrl_if.awaddr ),
+  .m_axi_awprot( ctrl_if.awprot ),
+  .m_axi_awvalid( ctrl_if.awvalid ),
+  .m_axi_awready( ctrl_if.awready ),
+  .m_axi_wdata( ctrl_if.wdata ),
+  .m_axi_wstrb( ctrl_if.wstrb ),
+  .m_axi_wvalid( ctrl_if.wvalid ),
+  .m_axi_wready( ctrl_if.wready ),
+  .m_axi_bresp( ctrl_if.bresp ),
+  .m_axi_bvalid( ctrl_if.bvalid ),
+  .m_axi_bready( ctrl_if.bready ),
+  .m_axi_araddr( ctrl_if.araddr ),
+  .m_axi_arprot( ctrl_if.arprot ),
+  .m_axi_arvalid( ctrl_if.arvalid ),
+  .m_axi_arready( ctrl_if.arready ),
+  .m_axi_rdata( ctrl_if.rdata ),
+  .m_axi_rresp( ctrl_if.rresp ),
+  .m_axi_rvalid( ctrl_if.rvalid ),
+  .m_axi_rready( ctrl_if.rready )  
+
+);
+
+initial begin
+    vip_mst = new("vip_mst", axi_vip_inst.inst.IF);
+    vip_mst.start_master();
+end
+
+axi4s_intf # (
+    .AXI_DATA_WIDTH(64),
+    .AXI_USER_WIDTH(16)
+) 
+hdr_out[2] ();      
+
+timing_engine dut (
+  .clk(clk),    
+  .pps(1'b0),
+
+  .ctrl_if(ctrl_if),
+  .start_of_cpi(),
+  .start_of_pulse(),
+  .timing_pulses(),
+  .hdr_out(hdr_out)
+);
+
+int fid_out;
+
+initial begin
+    reset = 1'b1;
+    clk = 1'b0;
+    $display($time, " << Starting the Simulation >>");
+
+    // Release Reset
+    repeat(25) @(posedge clk);
+    reset = 1'b0;
+    repeat(25) @(posedge clk);
+
+    // Set Control Regs
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 1, resp);   
+
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 16, resp);   
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, 4, resp);             
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0010, 0, 10, resp);
+
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0080, 0, 3, resp);       
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0084, 0, 4, resp);       
+
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0088, 0, 8, resp);       
+    vip_mst.AXI4LITE_WRITE_BURST(16'h008C, 0, 5, resp);          
+
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 0, resp);   
+
+    repeat(10000) @(posedge clk);
+    $display($time, " << Ending the Simulation >>");
+    $stop; 
+
+end
+
+endmodule
+`resetall

radar_alinx_kintex.xpr

@@ -56,7 +56,7 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="WTXSimLaunchSim" Val="100"/>
+    <Option Name="WTXSimLaunchSim" Val="110"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -561,8 +561,16 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/sim/tb_timing_engine.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PSRCDIR/sources_1/sim/tb_gen_ofdm.sv">
         <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>