fixing pulse gen bugs

This commit is contained in:
2025-11-19 20:57:42 -06:00
parent 5923ec0831
commit ef68f51d09
4 changed files with 125 additions and 5 deletions

View File

@@ -10,7 +10,7 @@ module pulse_generator #
input wire clk,
input wire rst,
input wire [COUNTER_BITS-1:0] pulse_length,
output wire start_of_pulse,
input wire start_of_pulse,
output wire pulse_out
);
@@ -22,9 +22,11 @@ assign pulse_out = pulse_active;
always @ (posedge clk) begin
if (rst == 1'b1) begin
pulse_cnt <= 0;
pulse_active <= 0;
end else begin
if (start_of_pulse) begin
pulse_active <= 1;
pulse_cnt <= pulse_length;
end
if (pulse_active) begin
@@ -38,7 +40,6 @@ always @ (posedge clk) begin
end
endmodule

View File

@@ -403,7 +403,7 @@ genvar j;
generate
for (j = 0; j < NUM_TIMING_PULSES; j = j + 1) begin
assign timing_pulses[j] = timing_pulses_i | reg_pulse_start[j][28];
assign timing_pulses[j] = timing_pulses_i[j] | reg_pulse_start[j][28];
always @ (posedge clk) begin
if (pri_cnt == reg_pulse_start[j][27:0]) begin
@@ -413,7 +413,7 @@ generate
end
end
pulse_generator (
pulse_generator pulse_generator_i(
.clk(clk),
.rst(rst),
.pulse_length(reg_pulse_width[j]),