fixing pulse gen bugs
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@@ -10,7 +10,7 @@ module pulse_generator #
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input wire clk,
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input wire rst,
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input wire [COUNTER_BITS-1:0] pulse_length,
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output wire start_of_pulse,
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input wire start_of_pulse,
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output wire pulse_out
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);
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@@ -22,9 +22,11 @@ assign pulse_out = pulse_active;
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always @ (posedge clk) begin
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if (rst == 1'b1) begin
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pulse_cnt <= 0;
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pulse_active <= 0;
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end else begin
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if (start_of_pulse) begin
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pulse_active <= 1;
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pulse_cnt <= pulse_length;
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end
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if (pulse_active) begin
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@@ -38,7 +40,6 @@ always @ (posedge clk) begin
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end
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endmodule
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@@ -403,7 +403,7 @@ genvar j;
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generate
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for (j = 0; j < NUM_TIMING_PULSES; j = j + 1) begin
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assign timing_pulses[j] = timing_pulses_i | reg_pulse_start[j][28];
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assign timing_pulses[j] = timing_pulses_i[j] | reg_pulse_start[j][28];
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always @ (posedge clk) begin
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if (pri_cnt == reg_pulse_start[j][27:0]) begin
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@@ -413,7 +413,7 @@ generate
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end
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end
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pulse_generator (
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pulse_generator pulse_generator_i(
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.clk(clk),
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.rst(rst),
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.pulse_length(reg_pulse_width[j]),
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