bkiedinger/castelion_radar_alinx_kintex
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bkiedinger@gmail.com
2025-05-20 20:33:12 -05:00
parent 8a1a6ea770
commit fcb291590b
104 changed files with 63299 additions and 45045 deletions
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68
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
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@@ -231,11 +231,18 @@ set_property PACKAGE_PIN A25 [get_ports fmc_spi0_miso]
set_property PACKAGE_PIN B27 [get_ports fmc_spi0_sck]
set_property PACKAGE_PIN B25 [get_ports fmc_spi0_ss]
set_property PULLUP TRUE [get_ports fmc_spi0_mosi]
set_property PULLUP TRUE [get_ports fmc_spi0_miso]
set_property PULLUP TRUE [get_ports fmc_spi0_sck]
set_property PACKAGE_PIN C22 [get_ports fmc_spi1_mosi]
set_property PACKAGE_PIN D20 [get_ports fmc_spi1_sck]
set_property PACKAGE_PIN C21 [get_ports fmc_spi1_ss]
set_property PACKAGE_PIN F27 [get_ports resetb]
set_property PULLUP TRUE [get_ports fmc_spi1_mosi]
set_property PULLUP TRUE [get_ports fmc_spi1_sck]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_mosi]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_miso]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_sck]
@@ -252,24 +259,42 @@ set_property IOSTANDARD LVDS [get_ports jesd_sysref_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports jesd_sysref_p]
set_property DQS_BIAS TRUE [get_ports jesd_sysref_p]
set_property DQS_BIAS TRUE [get_ports jesd_sysref_n]
create_clock -period 64.000 -name jesd_sysref [get_ports jesd_sysref_p]
set_property PACKAGE_PIN E28 [get_ports jesd_sync_in_p]
set_property PACKAGE_PIN D29 [get_ports jesd_sync_in_n]
set_property IOSTANDARD LVDS [get_ports jesd_sync_in_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports jesd_sync_in_p]
set_property PACKAGE_PIN E22 [get_ports jesd_sync_out_p]
set_property PACKAGE_PIN E23 [get_ports jesd_sync_out_n]
set_property IOSTANDARD LVDS [get_ports jesd_sync_out_p]
set_property PACKAGE_PIN K5 [get_ports jesd_qpll0_refclk_n]
set_property PACKAGE_PIN K6 [get_ports jesd_qpll0_refclk_p]
create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p]
#create_clock -period 4.0 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p]
#set_property PACKAGE_PIN P5 [get_ports jesd_qpll0_refclk_n]
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
# Works with the board at my house
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
#set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
#create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
# Works with the board Chris has
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_n]
create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
#create_clock -period 4.0 -name jesd_core_clk [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}]
#set_property PACKAGE_PIN H2 [get_ports {jesd_rxp_in[1]}]
@@ -424,34 +449,3 @@ set_property PACKAGE_PIN AE23 [get_ports {ddr_dq[7]}]
connect_debug_port u_ila_0/probe1 [get_nets [list pps_q2]]
connect_debug_port u_ila_0/probe3 [get_nets [list pps_red_i_1__0_n_0]]
connect_debug_port u_ila_0/probe4 [get_nets [list util_reg_i/spi_active]]
connect_debug_port u_ila_0/probe5 [get_nets [list util_reg_i/spi_shift_data]]
connect_debug_port u_ila_0/probe10 [get_nets [list util_reg_i/le_active]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list jesd_core_clk]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 1 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list microblaze_bd_i/jesd/util_ds_buf_1_IBUF_OUT]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]