bkiedinger/castelion_radar_alinx_kintex
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this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

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This commit is contained in:
bkiedinger@gmail.com
2025-04-25 06:26:07 -05:00
parent 729d034a13
commit 8a1a6ea770
30 changed files with 22794 additions and 22500 deletions
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3
python/data_recorder.py
View File

@@ -122,6 +122,9 @@ class DataRecorder:
self.write_queue.put(n)
offset += n
if offset >= len(self.buffer):
if self.port == 1234:
print('hmmm', n, offset, len(self.buffer))
offset = offset % len(self.buffer)
# print(offset)

14
python/radar_manager.py
View File

@@ -253,16 +253,20 @@ class RadarManager:
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x8, start_sample >> 2)
# Setup RX Strobe
self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, start_sample)
self.axi_write_register(TIMING_ENGINE_ADDR + 0x8C + i * 8, num_samples)
# self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, start_sample >> 2)
# self.axi_write_register(TIMING_ENGINE_ADDR + 0x8C + i * 8, num_samples >> 2)
# Just force the enable high all the time before we start running
self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, 0x1FFFFFFF)
def setup_tx(self, num_samples, start_sample):
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x4, num_samples >> 2)
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x8, start_sample >> 2)
# Setup TX Strobe
self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, start_sample)
self.axi_write_register(TIMING_ENGINE_ADDR + 0x84, num_samples)
# self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, start_sample >> 2)
# self.axi_write_register(TIMING_ENGINE_ADDR + 0x84, num_samples >> 2)
# Just force the enable high all the time before we start running
self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, 0x1FFFFFFF)
def start_running(self):
for i in range(NUM_RX):
@@ -274,7 +278,9 @@ class RadarManager:
self.axi_write_register(TIMING_ENGINE_ADDR + 0x0, 1) # Timing Engine Reset
for i in range(NUM_RX):
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x0, 1) # RX Reset
self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, 0x0FFFFFF) # Clear RX Enable
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x0, 1) # TX Reset
self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, 0x0FFFFFF) # Clear TX Enable
def setup_rf_attenuators(self, rf_atten):
self.rf_spi_write((1 << 0), 6, rf_atten[0]) # TX0 RF (ADRF5730)

187
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
View File

@@ -11,6 +11,7 @@ set_property CFGBVS VCCO [current_design]
#-------------------------------------------
set_false_path -from [get_cells util_reg_i/reg_*]
set_false_path -from [get_cells timing_engine_i/reg_*]
set_false_path -from [get_cells timing_engine_i/genblk1*reg_*]
set_false_path -from [get_cells timing_engine_i/system_time_start_of_cpi*]
set_false_path -from [get_cells *digital_rx_chain_i/reg_*]
set_false_path -from [get_cells waveform_gen_i/reg_*]
@@ -32,32 +33,67 @@ set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_200_n]
# set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_p]
# set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_n]
#-------------------------------------------
# I2C
#-------------------------------------------
set_property PACKAGE_PIN P24 [get_ports i2c_scl]
set_property PACKAGE_PIN P25 [get_ports i2c_sda]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda]
#-------------------------------------------
# RF Attenautors
#-------------------------------------------
set_property PACKAGE_PIN G25 [get_ports tx0_rf_attn_sin]
set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk]
set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le]
set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin]
set_property PACKAGE_PIN P23 [get_ports tx1_rf_attn_clk]
set_property PACKAGE_PIN R23 [get_ports tx1_rf_attn_le]
set_property PACKAGE_PIN K25 [get_ports txlo_drv_en]
# FMC2
#set_property PACKAGE_PIN G25 [get_ports tx0_rf_attn_sin]
#set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk]
#set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le]
#set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin]
#set_property PACKAGE_PIN P23 [get_ports tx1_rf_attn_clk]
#set_property PACKAGE_PIN R23 [get_ports tx1_rf_attn_le]
#set_property PACKAGE_PIN K25 [get_ports txlo_drv_en]
set_property PACKAGE_PIN R25 [get_ports rx0_rf_attn_sin]
set_property PACKAGE_PIN T25 [get_ports rx0_rf_attn_clk]
set_property PACKAGE_PIN T24 [get_ports rx0_rf_attn_le]
set_property PACKAGE_PIN AM11 [get_ports rx0_if_attn_sin]
set_property PACKAGE_PIN AF13 [get_ports rx0_if_attn_clk]
set_property PACKAGE_PIN AE13 [get_ports rx0_if_attn_le]
set_property PACKAGE_PIN AN11 [get_ports rx0_lna_en]
#set_property PACKAGE_PIN R25 [get_ports rx0_rf_attn_sin]
#set_property PACKAGE_PIN T25 [get_ports rx0_rf_attn_clk]
#set_property PACKAGE_PIN T24 [get_ports rx0_rf_attn_le]
#set_property PACKAGE_PIN AM11 [get_ports rx0_if_attn_sin]
#set_property PACKAGE_PIN AF13 [get_ports rx0_if_attn_clk]
#set_property PACKAGE_PIN AE13 [get_ports rx0_if_attn_le]
#set_property PACKAGE_PIN AN11 [get_ports rx0_lna_en]
set_property PACKAGE_PIN J24 [get_ports rx1_rf_attn_sin]
set_property PACKAGE_PIN G27 [get_ports rx1_rf_attn_clk]
set_property PACKAGE_PIN H27 [get_ports rx1_rf_attn_le]
set_property PACKAGE_PIN K26 [get_ports rx1_if_attn_sin]
set_property PACKAGE_PIN L27 [get_ports rx1_if_attn_clk]
set_property PACKAGE_PIN M27 [get_ports rx1_if_attn_le]
set_property PACKAGE_PIN K27 [get_ports rx1_lna_en]
#set_property PACKAGE_PIN J24 [get_ports rx1_rf_attn_sin]
#set_property PACKAGE_PIN G27 [get_ports rx1_rf_attn_clk]
#set_property PACKAGE_PIN H27 [get_ports rx1_rf_attn_le]
#set_property PACKAGE_PIN K26 [get_ports rx1_if_attn_sin]
#set_property PACKAGE_PIN L27 [get_ports rx1_if_attn_clk]
#set_property PACKAGE_PIN M27 [get_ports rx1_if_attn_le]
#set_property PACKAGE_PIN K27 [get_ports rx1_lna_en]
# FMC1
set_property PACKAGE_PIN AE28 [get_ports tx0_rf_attn_sin]
set_property PACKAGE_PIN AB34 [get_ports tx0_rf_attn_clk]
set_property PACKAGE_PIN AA34 [get_ports tx0_rf_attn_le]
set_property PACKAGE_PIN AC34 [get_ports tx1_rf_attn_sin]
set_property PACKAGE_PIN AF34 [get_ports tx1_rf_attn_clk]
set_property PACKAGE_PIN AE33 [get_ports tx1_rf_attn_le]
set_property PACKAGE_PIN AD34 [get_ports txlo_drv_en]
set_property PACKAGE_PIN AF33 [get_ports rx0_rf_attn_sin]
set_property PACKAGE_PIN AG30 [get_ports rx0_rf_attn_clk]
set_property PACKAGE_PIN AF30 [get_ports rx0_rf_attn_le]
set_property PACKAGE_PIN U21 [get_ports rx0_if_attn_sin]
set_property PACKAGE_PIN AB20 [get_ports rx0_if_attn_clk]
set_property PACKAGE_PIN AA20 [get_ports rx0_if_attn_le]
set_property PACKAGE_PIN U22 [get_ports rx0_lna_en]
set_property PACKAGE_PIN AC28 [get_ports rx1_rf_attn_sin]
set_property PACKAGE_PIN AE30 [get_ports rx1_rf_attn_clk]
set_property PACKAGE_PIN AD29 [get_ports rx1_rf_attn_le]
set_property PACKAGE_PIN AC33 [get_ports rx1_if_attn_sin]
set_property PACKAGE_PIN AF32 [get_ports rx1_if_attn_clk]
set_property PACKAGE_PIN AE32 [get_ports rx1_if_attn_le]
set_property PACKAGE_PIN AD33 [get_ports rx1_lna_en]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_clk]
@@ -214,6 +250,8 @@ set_property PACKAGE_PIN D25 [get_ports jesd_sysref_n]
set_property IOSTANDARD LVDS [get_ports jesd_sysref_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports jesd_sysref_p]
set_property DQS_BIAS TRUE [get_ports jesd_sysref_p]
set_property DQS_BIAS TRUE [get_ports jesd_sysref_n]
set_property PACKAGE_PIN K5 [get_ports jesd_qpll0_refclk_n]
set_property PACKAGE_PIN K6 [get_ports jesd_qpll0_refclk_p]
@@ -222,13 +260,15 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
#set_property PACKAGE_PIN P5 [get_ports jesd_qpll0_refclk_n]
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}]
@@ -396,108 +436,21 @@ connect_debug_port u_ila_0/probe5 [get_nets [list util_reg_i/spi_shift_data]]
connect_debug_port u_ila_0/probe10 [get_nets [list util_reg_i/le_active]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list microblaze_bd_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1]]
connect_debug_port u_ila_0/clk [get_nets [list jesd_core_clk]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {util_reg_i/spi_bit_cnt_reg[0]} {util_reg_i/spi_bit_cnt_reg[1]} {util_reg_i/spi_bit_cnt_reg[2]} {util_reg_i/spi_bit_cnt_reg[3]} {util_reg_i/spi_bit_cnt_reg[4]} {util_reg_i/spi_bit_cnt_reg[5]} {util_reg_i/spi_bit_cnt_reg[6]} {util_reg_i/spi_bit_cnt_reg[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {util_reg_i/reg_spi_data[0]} {util_reg_i/reg_spi_data[1]} {util_reg_i/reg_spi_data[2]} {util_reg_i/reg_spi_data[3]} {util_reg_i/reg_spi_data[4]} {util_reg_i/reg_spi_data[5]} {util_reg_i/reg_spi_data[6]} {util_reg_i/reg_spi_data[7]} {util_reg_i/reg_spi_data[8]} {util_reg_i/reg_spi_data[9]} {util_reg_i/reg_spi_data[10]} {util_reg_i/reg_spi_data[11]} {util_reg_i/reg_spi_data[12]} {util_reg_i/reg_spi_data[13]} {util_reg_i/reg_spi_data[14]} {util_reg_i/reg_spi_data[15]} {util_reg_i/reg_spi_data[16]} {util_reg_i/reg_spi_data[17]} {util_reg_i/reg_spi_data[18]} {util_reg_i/reg_spi_data[19]} {util_reg_i/reg_spi_data[20]} {util_reg_i/reg_spi_data[21]} {util_reg_i/reg_spi_data[22]} {util_reg_i/reg_spi_data[23]} {util_reg_i/reg_spi_data[24]} {util_reg_i/reg_spi_data[25]} {util_reg_i/reg_spi_data[26]} {util_reg_i/reg_spi_data[27]} {util_reg_i/reg_spi_data[28]} {util_reg_i/reg_spi_data[29]} {util_reg_i/reg_spi_data[30]} {util_reg_i/reg_spi_data[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {util_reg_i/spi_clk_cnt_reg[0]} {util_reg_i/spi_clk_cnt_reg[1]} {util_reg_i/spi_clk_cnt_reg[2]} {util_reg_i/spi_clk_cnt_reg[3]} {util_reg_i/spi_clk_cnt_reg[4]} {util_reg_i/spi_clk_cnt_reg[5]} {util_reg_i/spi_clk_cnt_reg[6]} {util_reg_i/spi_clk_cnt_reg[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 5 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {util_reg_i/le_count_reg[0]} {util_reg_i/le_count_reg[1]} {util_reg_i/le_count_reg[2]} {util_reg_i/le_count_reg[3]} {util_reg_i/le_count_reg[4]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list util_reg_i/start_spi_transaction]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list tx0_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list tx0_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list tx0_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list rx0_if_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list rx0_if_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list rx0_if_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list rx0_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list rx0_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list rx0_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list rx1_if_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list rx1_if_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list rx1_if_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list rx1_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list rx1_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list rx1_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list tx1_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list tx1_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list tx1_rf_attn_sin_OBUF]]
set_property port_width 1 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list microblaze_bd_i/jesd/util_ds_buf_1_IBUF_OUT]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]

5381
radar_alinx_kintex.srcs/sources_1/bd/microblaze_bd/microblaze_bd.bd
View File

File diff suppressed because it is too large Load Diff

45
radar_alinx_kintex.srcs/sources_1/hdl/pulse_generator.v Executable file
View File

@@ -0,0 +1,45 @@
`resetall
`timescale 1ns / 1ps
`default_nettype none
module pulse_generator #
(
parameter integer COUNTER_BITS = 28
)
(
input wire clk,
input wire rst,
input wire [COUNTER_BITS-1:0] pulse_length,
output wire start_of_pulse,
output wire pulse_out
);
reg [COUNTER_BITS-1:0] pulse_cnt;
reg pulse_active;
assign pulse_out = pulse_active;
always @ (posedge clk) begin
if (rst == 1'b1) begin
pulse_cnt <= 0;
end else begin
if (start_of_pulse) begin
pulse_active <= 1;
end
if (pulse_active) begin
pulse_cnt <= pulse_cnt - 1;
if (pulse_cnt == 0) begin
pulse_active <= 0;
end
end
end
end
endmodule
`resetall

15
radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v
View File

@@ -83,8 +83,8 @@ reg [27:0] reg_pri;
reg [27:0] reg_num_pulses;
reg [27:0] reg_inter_cpi;
reg [31:0] reg_pps_sec_set;
reg [31:0] reg_pulse_width [NUM_TIMING_PULSES-1:0];
reg [31:0] reg_pulse_start [NUM_TIMING_PULSES-1:0];
reg [27:0] reg_pulse_width [NUM_TIMING_PULSES-1:0];
reg [28:0] reg_pulse_start [NUM_TIMING_PULSES-1:0];
reg [63:0] system_time;
reg [63:0] pps_frac_sec;
@@ -141,7 +141,7 @@ generate
for (gen_reg = 0; gen_reg < NUM_TIMING_PULSES; gen_reg = gen_reg + 1) begin
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_pulse_start[gen_reg] <= 0;
reg_pulse_start[gen_reg] <= 28'hFFFFFF;
end else if (wren && waddr[11:0] == ('h080 + gen_reg*8)) begin
reg_pulse_start[gen_reg] <= wdata;
end
@@ -396,14 +396,17 @@ end
// ------------------------------
// Pulse Generators
// ------------------------------
reg [NUM_TIMING_PULSES-1:0] pulse_start;
reg [NUM_TIMING_PULSES-1:0] pulse_start;
reg [NUM_TIMING_PULSES-1:0] timing_pulses_i;
genvar j;
generate
for (j = 0; j < NUM_TIMING_PULSES; j = j + 1) begin
assign timing_pulses[j] = timing_pulses_i | reg_pulse_start[j][28];
always @ (posedge clk) begin
if (pri_cnt == reg_pulse_start[j]) begin
if (pri_cnt == reg_pulse_start[j][27:0]) begin
pulse_start[j] <= 1;
end else begin
pulse_start[j] <= 0;
@@ -415,7 +418,7 @@ generate
.rst(rst),
.pulse_length(reg_pulse_width[j]),
.start_of_pulse(pulse_start[j]),
.pulse_out(timing_pulses[j])
.pulse_out(timing_pulses_i[j])
);
end

31
radar_alinx_kintex.srcs/sources_1/hdl/top.v
View File

@@ -42,6 +42,10 @@ module top #
output wire fmc_power_en,
input wire pps,
// I2C
inout wire i2c_scl,
inout wire i2c_sda,
// RF Control
output wire tx0_rf_attn_sin, //ADRF5730
output wire tx0_rf_attn_clk, //ADRF5730
@@ -286,6 +290,26 @@ module top #
.T(fmc_spi1_ss_t));
// I2C For changing regulator voltage
wire i2c_scl_i;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_i;
wire i2c_sda_o;
wire i2c_sda_t;
IOBUF i2c_scl_iobuf
(.I(i2c_scl_o),
.IO(i2c_scl),
.O(i2c_scl_i),
.T(i2c_scl_t));
IOBUF i2c_sda_iobuf
(.I(i2c_sda_o),
.IO(i2c_sda),
.O(i2c_sda_i),
.T(i2c_sda_t));
// ------------------------------
// BD
// ------------------------------
@@ -370,6 +394,13 @@ module top #
microblaze_bd microblaze_bd_i
(
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
.STARTUP_IO_cfgclk(),
.STARTUP_IO_cfgmclk(),
.STARTUP_IO_eos(),

4
radar_alinx_kintex.srcs/sources_1/ip/axis_switch_0/axis_switch_0.xci
View File

@@ -350,9 +350,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/clock_converter/clock_converter.xci
View File

@@ -42,9 +42,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/data_fifo/data_fifo.xci
View File

@@ -60,9 +60,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci
View File

@@ -42,9 +42,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci
View File

@@ -39,9 +39,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

32
radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci
View File

@@ -23,7 +23,7 @@
"INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"INS_LOSS_NYQ": [ { "value": "20", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -31,18 +31,18 @@
"PCIE_USERCLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_PLL_TYPE": [ { "value": "QPLL0", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ],
"RX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_PLL_TYPE": [ { "value": "QPLL0", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -50,7 +50,7 @@
"RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
"RX_JTOL_FC": [ { "value": "6.1862627", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ],
@@ -168,7 +168,7 @@
"LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ],
"ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PRESET": [ { "value": "GTH-10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
@@ -181,9 +181,9 @@
"SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"TXPROGDIV_FREQ_SOURCE": [ { "value": "QPLL0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -830,9 +830,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@@ -874,10 +874,10 @@
"gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gthrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gthrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll0refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll1clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll1refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll0clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll1clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll1refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxgearboxslip_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"txheader_in": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
"txsequence_in": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ],

20
radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci
View File

@@ -23,7 +23,7 @@
"INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"INS_LOSS_NYQ": [ { "value": "20", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -32,17 +32,17 @@
"TX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_PLL_TYPE": [ { "value": "QPLL0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ],
"RX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_PLL_TYPE": [ { "value": "QPLL0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -50,7 +50,7 @@
"RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
"RX_JTOL_FC": [ { "value": "6.1862627", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ],
@@ -168,7 +168,7 @@
"LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ],
"ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PRESET": [ { "value": "GTH-10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "14", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
@@ -181,9 +181,9 @@
"SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"TXPROGDIV_FREQ_SOURCE": [ { "value": "QPLL0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -830,9 +830,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/hdr_fifo/hdr_fifo.xci
View File

@@ -60,9 +60,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

20
radar_alinx_kintex.srcs/sources_1/ip/hdr_mem/hdr_mem.xci
View File

@@ -34,17 +34,17 @@
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Operating_Mode_A": [ { "value": "NO_CHANGE", "resolve_type": "user", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Operating_Mode_A": [ { "value": "NO_CHANGE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ],
"Write_Width_B": [ { "value": "64", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Read_Width_B": [ { "value": "64", "resolve_type": "user", "usage": "all" } ],
"Read_Width_B": [ { "value": "64", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_B": [ { "value": "Use_ENB_Pin", "resolve_type": "user", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -66,10 +66,10 @@
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -166,9 +166,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci
View File

@@ -60,9 +60,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

18
radar_alinx_kintex.srcs/sources_1/ip/wf_memory/wf_memory.xci
View File

@@ -14,7 +14,7 @@
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -34,17 +34,17 @@
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "resolve_type": "user", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ],
"Write_Width_B": [ { "value": "128", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Read_Width_B": [ { "value": "128", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
"Enable_B": [ { "value": "Use_ENB_Pin", "resolve_type": "user", "usage": "all" } ],
"Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -66,10 +66,10 @@
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Write_Rate": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -166,9 +166,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/width_converter/width_converter.xci
View File

@@ -39,9 +39,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

BIN
radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
View File

Binary file not shown.

510
radar_alinx_kintex.xpr
View File

@@ -7,7 +7,7 @@
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="c179ea77804d47eabf9d7773e858daa9"/>
<Option Name="Part" Val="xcku040-ffva1156-2-i"/>
<Option Name="Part" Val="xcku040-ffva1156-1-c"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
@@ -493,6 +493,30 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/clock_converter/clock_converter.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/data_fifo/data_fifo.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/width_converter/width_converter.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="top"/>
@@ -544,53 +568,8 @@
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="data_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/data_fifo" RelGenDir="$PGENDIR/data_fifo">
<File Path="$PSRCDIR/sources_1/ip/data_fifo/data_fifo.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="data_fifo"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="width_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/width_converter" RelGenDir="$PGENDIR/width_converter">
<File Path="$PSRCDIR/sources_1/ip/width_converter/width_converter.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="width_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="clock_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clock_converter" RelGenDir="$PGENDIR/clock_converter">
<File Path="$PSRCDIR/sources_1/ip/clock_converter/clock_converter.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="clock_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="wf_memory" Type="BlockSrcs" RelSrcDir="$PSRCDIR/wf_memory" RelGenDir="$PGENDIR/wf_memory">
<File Path="$PSRCDIR/sources_1/ip/wf_memory/wf_memory.xci">
<FileSet Name="microblaze_bd" Type="BlockSrcs" RelSrcDir="$PSRCDIR/microblaze_bd" RelGenDir="$PGENDIR/microblaze_bd">
<File Path="$PSRCDIR/sources_1/bd/microblaze_bd/microblaze_bd.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@@ -598,91 +577,7 @@
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="wf_memory"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="eth_xcvr_gt_full" Type="BlockSrcs" RelSrcDir="$PSRCDIR/eth_xcvr_gt_full" RelGenDir="$PGENDIR/eth_xcvr_gt_full">
<File Path="$PSRCDIR/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="eth_xcvr_gt_full"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="eth_xcvr_gt_channel" Type="BlockSrcs" RelSrcDir="$PSRCDIR/eth_xcvr_gt_channel" RelGenDir="$PGENDIR/eth_xcvr_gt_channel">
<File Path="$PSRCDIR/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="eth_xcvr_gt_channel"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pulse_buffer_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pulse_buffer_fifo" RelGenDir="$PGENDIR/pulse_buffer_fifo">
<File Path="$PSRCDIR/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="pulse_buffer_fifo"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="dig_rx_dwidth_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dig_rx_dwidth_converter" RelGenDir="$PGENDIR/dig_rx_dwidth_converter">
<File Path="$PSRCDIR/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="dig_rx_dwidth_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="dig_rx_clock_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dig_rx_clock_converter" RelGenDir="$PGENDIR/dig_rx_clock_converter">
<File Path="$PSRCDIR/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="dig_rx_clock_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="hdr_mem" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hdr_mem" RelGenDir="$PGENDIR/hdr_mem">
<File Path="$PSRCDIR/sources_1/ip/hdr_mem/hdr_mem.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="hdr_mem"/>
<Option Name="TopModule" Val="microblaze_bd"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
@@ -701,6 +596,104 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="hdr_mem" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hdr_mem" RelGenDir="$PGENDIR/hdr_mem">
<File Path="$PSRCDIR/sources_1/ip/hdr_mem/hdr_mem.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="hdr_mem"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="dig_rx_clock_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dig_rx_clock_converter" RelGenDir="$PGENDIR/dig_rx_clock_converter">
<File Path="$PSRCDIR/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="dig_rx_clock_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="dig_rx_dwidth_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dig_rx_dwidth_converter" RelGenDir="$PGENDIR/dig_rx_dwidth_converter">
<File Path="$PSRCDIR/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="dig_rx_dwidth_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pulse_buffer_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pulse_buffer_fifo" RelGenDir="$PGENDIR/pulse_buffer_fifo">
<File Path="$PSRCDIR/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="pulse_buffer_fifo"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="eth_xcvr_gt_channel" Type="BlockSrcs" RelSrcDir="$PSRCDIR/eth_xcvr_gt_channel" RelGenDir="$PGENDIR/eth_xcvr_gt_channel">
<File Path="$PSRCDIR/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="eth_xcvr_gt_channel"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="eth_xcvr_gt_full" Type="BlockSrcs" RelSrcDir="$PSRCDIR/eth_xcvr_gt_full" RelGenDir="$PGENDIR/eth_xcvr_gt_full">
<File Path="$PSRCDIR/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="eth_xcvr_gt_full"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="wf_memory" Type="BlockSrcs" RelSrcDir="$PSRCDIR/wf_memory" RelGenDir="$PGENDIR/wf_memory">
<File Path="$PSRCDIR/sources_1/ip/wf_memory/wf_memory.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="wf_memory"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="hdr_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hdr_fifo" RelGenDir="$PGENDIR/hdr_fifo">
<File Path="$PSRCDIR/sources_1/ip/hdr_fifo/hdr_fifo.xci">
<FileInfo>
@@ -715,20 +708,6 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="microblaze_bd" Type="BlockSrcs" RelSrcDir="$PSRCDIR/microblaze_bd" RelGenDir="$PGENDIR/microblaze_bd">
<File Path="$PSRCDIR/sources_1/bd/microblaze_bd/microblaze_bd.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="microblaze_bd"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@@ -752,7 +731,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="19">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-1-c" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -762,7 +741,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="data_fifo_synth_1" Type="Ft3:Synth" SrcSet="data_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="data_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/data_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/data_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/data_fifo_synth_1">
<Run Id="microblaze_bd_synth_1" Type="Ft3:Synth" SrcSet="microblaze_bd" Part="xcku040-ffva1156-1-c" ConstrsSet="microblaze_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/microblaze_bd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -772,7 +751,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="width_converter_synth_1" Type="Ft3:Synth" SrcSet="width_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="width_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/width_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/width_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/width_converter_synth_1">
<Run Id="axis_switch_0_synth_1" Type="Ft3:Synth" SrcSet="axis_switch_0" Part="xcku040-ffva1156-1-c" ConstrsSet="axis_switch_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axis_switch_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -782,7 +761,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clock_converter_synth_1" Type="Ft3:Synth" SrcSet="clock_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="clock_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clock_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clock_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/clock_converter_synth_1">
<Run Id="hdr_mem_synth_1" Type="Ft3:Synth" SrcSet="hdr_mem" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_mem" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_mem_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -792,7 +771,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="wf_memory_synth_1" Type="Ft3:Synth" SrcSet="wf_memory" Part="xcku040-ffva1156-2-i" ConstrsSet="wf_memory" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/wf_memory_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1">
<Run Id="dig_rx_clock_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_clock_converter" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_clock_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_clock_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -802,7 +781,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_full_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_full" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_full" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_full_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1">
<Run Id="dig_rx_dwidth_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_dwidth_converter" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_dwidth_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_dwidth_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -812,7 +791,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_channel_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_channel" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_channel" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_channel_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1">
<Run Id="pulse_buffer_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_fifo" Part="xcku040-ffva1156-1-c" ConstrsSet="pulse_buffer_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pulse_buffer_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -822,7 +801,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pulse_buffer_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pulse_buffer_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1">
<Run Id="eth_xcvr_gt_channel_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_channel" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_channel" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_channel_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -832,7 +811,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_dwidth_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_dwidth_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_dwidth_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_dwidth_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1">
<Run Id="eth_xcvr_gt_full_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_full" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_full" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_full_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -842,7 +821,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_clock_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_clock_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_clock_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_clock_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1">
<Run Id="wf_memory_synth_1" Type="Ft3:Synth" SrcSet="wf_memory" Part="xcku040-ffva1156-1-c" ConstrsSet="wf_memory" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/wf_memory_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -852,7 +831,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_mem_synth_1" Type="Ft3:Synth" SrcSet="hdr_mem" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_mem" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_mem_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1">
<Run Id="hdr_fifo_synth_1" Type="Ft3:Synth" SrcSet="hdr_fifo" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -862,37 +841,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axis_switch_0_synth_1" Type="Ft3:Synth" SrcSet="axis_switch_0" Part="xcku040-ffva1156-2-i" ConstrsSet="axis_switch_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axis_switch_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_fifo_synth_1" Type="Ft3:Synth" SrcSet="hdr_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="microblaze_bd_synth_1" Type="Ft3:Synth" SrcSet="microblaze_bd" Part="xcku040-ffva1156-2-i" ConstrsSet="microblaze_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/microblaze_bd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -910,7 +859,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="data_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="data_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="data_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/data_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/data_fifo_impl_1">
<Run Id="microblaze_bd_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="microblaze_bd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="microblaze_bd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -927,7 +876,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="width_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="width_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="width_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/width_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/width_converter_impl_1">
<Run Id="axis_switch_0_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="axis_switch_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axis_switch_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -944,7 +893,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clock_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="clock_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clock_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clock_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/clock_converter_impl_1">
<Run Id="hdr_mem_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_mem" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_mem_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -961,7 +910,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="wf_memory_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="wf_memory" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="wf_memory_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1">
<Run Id="dig_rx_clock_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_clock_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_clock_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -978,7 +927,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_full_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_full" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_full_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1">
<Run Id="dig_rx_dwidth_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_dwidth_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_dwidth_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -995,7 +944,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_channel_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_channel" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_channel_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1">
<Run Id="pulse_buffer_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="pulse_buffer_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pulse_buffer_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1012,7 +961,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pulse_buffer_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pulse_buffer_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1">
<Run Id="eth_xcvr_gt_channel_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_channel" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_channel_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1029,7 +978,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_dwidth_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_dwidth_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_dwidth_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1">
<Run Id="eth_xcvr_gt_full_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_full" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_full_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1046,7 +995,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_clock_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_clock_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_clock_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1">
<Run Id="wf_memory_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="wf_memory" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="wf_memory_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1063,58 +1012,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_mem_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_mem" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_mem_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axis_switch_0_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="axis_switch_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axis_switch_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="microblaze_bd_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="microblaze_bd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="microblaze_bd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_impl_1">
<Run Id="hdr_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1132,62 +1030,6 @@
<RQSFiles/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1306]"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1271]"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1306]"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1271]"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
@@ -1888,6 +1730,20 @@
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1306]"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="59"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
@@ -1902,6 +1758,48 @@
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1271]"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="60"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1306]"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="61"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1271]"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="62"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>
<MsgAttr Name="Limit" Val="-1"/>

4
vitis/radar/_ide/launch/IBERT.launch
View File

@@ -18,7 +18,7 @@
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uipl.powerup" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{&quot;microblaze_0&quot;:{&quot;xilinx.tcf.application&quot;:&quot;Debug/radar.elf&quot;,&quot;xilinx.tcf.datafiles&quot;:&quot;&quot;,&quot;xilinx.tcf.no_download&quot;:false,&quot;xilinx.tcf.profile_enabled&quot;:false,&quot;xilinx.tcf.profile_frequency&quot;:&quot;10000&quot;,&quot;xilinx.tcf.profile_non_int_frequency&quot;:&quot;150000000&quot;,&quot;xilinx.tcf.profile_non_int_high_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_low_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_use_count_instr&quot;:false,&quot;xilinx.tcf.profile_non_int_use_cumulate&quot;:false,&quot;xilinx.tcf.profile_non_intrusive_support&quot;:false,&quot;xilinx.tcf.profile_store_address&quot;:&quot;0x0&quot;,&quot;xilinx.tcf.profile_use_intrusive&quot;:false,&quot;xilinx.tcf.project&quot;:&quot;radar&quot;,&quot;xilinx.tcf.relocate&quot;:false,&quot;xilinx.tcf.relocate_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.reset&quot;:true,&quot;xilinx.tcf.stop_at_entry&quot;:false}}"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.selection" value="microblaze_0"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="true"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproject.name" value="radar"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uips.device" value="Auto Detect"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uips7.init" value="false"/>
@@ -26,7 +26,7 @@
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.apu" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.lock.step" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.rpu" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.system" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.system" value="true"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uitarget.peer" value="Local"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.active.build.config" value="Debug"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.application.type" value=""/>

5
vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_device.c
View File

@@ -17,7 +17,8 @@
#include "adi_ad9081_hal.h"
#define DEFAULT_DAC_FULLSCALE_CURRENT 26000 /*26mA*/
//#define DEFAULT_DAC_FULLSCALE_CURRENT 26000 /*26mA*/
#define DEFAULT_DAC_FULLSCALE_CURRENT 37000 /*37mA*/
/*============= C O D E ====================*/
int32_t adi_ad9081_device_boot_pre_clock(adi_ad9081_device_t *device)
{
@@ -1339,4 +1340,4 @@ int32_t adi_ad9081_device_startup_rx(adi_ad9081_device_t *device, uint8_t cddcs,
return API_CMS_ERROR_OK;
}
/*! @} */
/*! @} */

2
vitis/radar/src/ad9081_app_helper.c
View File

@@ -37,8 +37,6 @@ extern uint8_t rx_fddc_dcm[][8];
extern uint8_t rx_cddc_c2r[][4];
extern uint8_t rx_fddc_c2r[8];
extern uint8_t jtx_logiclane_mapping_pe_brd[2][8];
extern uint8_t jtx_logiclane_mapping_ce_brd[2][8];
extern adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2];
extern adi_cms_jesd_param_t jrx_param[];

42
vitis/radar/src/data_converter_setup.c
View File

@@ -32,9 +32,6 @@ extern uint8_t rx_fddc_dcm[][8];
extern uint8_t rx_cddc_c2r[][4];
extern uint8_t rx_fddc_c2r[8];
extern uint8_t jtx_logiclane_mapping_pe_brd[2][8];
extern uint8_t jtx_logiclane_mapping_ce_brd[2][8];
extern adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2];
extern adi_cms_jesd_param_t jrx_param[];
extern adi_cms_jesd_param_t jtx_param[][2];
@@ -73,7 +70,7 @@ void setup_data_converter() {
hmc7044_init();
// select use case
int uc = 0;
int uc = 1;
uint64_t app_jrx_lane_rate = 0;
uint64_t app_jtx_lane_rate[2] = {0};
@@ -153,7 +150,8 @@ void setup_data_converter() {
}
},
.clk_info = {
.sysref_mode = SYSREF_NONE,
// .sysref_mode = SYSREF_NONE,
.sysref_mode = SYSREF_CONT,
}
};
@@ -210,6 +208,7 @@ void setup_data_converter() {
hmc_out_ch &= ~(HMC7044_OP_CH_3 | HMC7044_OP_CH_13);
hmc_out_204c[3] = 0;
hmc_out_204c[13] = 0;
xil_printf("Disabling Sysref!!!!!!!\r\n");
}
if (err = adi_hmc7044_device_init(&hmc7044_dev), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
@@ -377,17 +376,17 @@ void setup_data_converter() {
printf("APP: Phase offset between incoming SYSREF and internal LMFC/LEMC: %d DAC clock units\n", phase);
// printf("APP: JESD RX Synchronization Mode: %s\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
// /* Power down Sysref Receiver circuitry*/
// if (err = adi_ad9081_jesd_sysref_input_mode_set(&ad9081_dev, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, COUPLING_AC), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// /* Perform oneshot sync */
// if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 0), err != API_CMS_ERROR_OK){
// if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
// printf("APP: JESD Oneshot Synchronization Not Completed");
// }
// error_print(__LINE__, err);
// }
printf("APP: JESD RX Synchronization Mode: %s\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
/* Power down Sysref Receiver circuitry*/
if (err = adi_ad9081_jesd_sysref_input_mode_set(&ad9081_dev, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, COUPLING_AC), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Perform oneshot sync */
if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 0), err != API_CMS_ERROR_OK){
if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
printf("APP: JESD Oneshot Synchronization Not Completed");
}
error_print(__LINE__, err);
}
/* SYSTEM Link Bring Up Sequenece
* Check AD9081 JESD PLL Lock Status
@@ -543,12 +542,23 @@ void setup_data_converter() {
vTaskDelay(100);
}
xil_printf("* Block sync achieved\r\n");
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
xil_printf("Wait for Extended Multiblock lock\r\n");
val = 0;
while ((val & STATUS_EMB_LOCK_BIT) != STATUS_EMB_LOCK_BIT) {
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
xil_printf("RX EMB: 0x%x\r\n", Xil_In32(JESD_RX + CTRL_MB_IN_EMB));
// for (int i = 0; i < 8; i++) {
// // Clear Error Counts
// uint32_t err_cnt = Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x10);
// xil_printf(" Lane %d STAT_RX_ERROR_CNT0 = 0x%x\r\n", err_cnt);
// }
vTaskDelay(100);
}
xil_printf("* Extended Multiblock lock achieved\r\n");

8
vitis/radar/src/hmc7044/src/adi_hmc7044_device.c
View File

@@ -502,7 +502,15 @@ int32_t adi_hmc7044_clk_config(adi_hmc7044_device_t *device, adi_hmc7044_clk_in_
/*Configure Clockout Frequencies*/
for (i = 0; i < HMC7044_NOF_OP_CH; i++) {
if (i == 10) {
xil_printf("Clk Out %d LVDS \r\n", i);
hmc_driver_config.mode = SIGNAL_LVDS;
} else if (i == 13) {
xil_printf("Clk Out %d LVDS \r\n", i);
hmc_driver_config.mode = SIGNAL_LVDS;
hmc_driver_config.mode = SIGNAL_LVDS;
} else if (i == 6) {
xil_printf("Clk Out %d LVDS \r\n", i);
hmc_driver_config.mode = SIGNAL_LVDS;
} else {
hmc_driver_config.mode = SIGNAL_CML;
}

3
vitis/radar/src/main.c
View File

@@ -115,6 +115,7 @@ void main_task( void *pvParameters ) {
while (1) {
toggleBit(0x40050008, 0); // Toggle LED
vTaskDelay(100);
}
}
@@ -133,7 +134,7 @@ int main(void) {
xTaskCreate( main_task,
( const char * ) "main",
0x10000,
0x20000,
NULL,
TASK_PRIORITY_MAIN,
NULL );

38
vitis/radar/src/uc_settings.c
View File

@@ -41,11 +41,9 @@ build a usecase parameters for a custom application.
*
*/
uint64_t clk_hz[][4] = {
/*dev_ref, fpga_ref, dac_clk, adc_clk */ /* UC, JESD, Crystal type, Lane rate, Comments */
// { 125e6, 275e6, 6000e6, 2000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
// { 125e6, 275e6, 8000e6, 4000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
// { 118.75e6, 237.5e6, 11400e6, 3800e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
{ 93.75e6, 187.5e6, 9000e6, 3000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
/*dev_ref, fpga_ref, dac_clk, adc_clk */
{ 93.75e6, 187.5e6, 9000e6, 3000e6 },
{ 118.75e6, 237.5e6, 11400e6, 3800e6 },
}; // 204B
#if !defined(AD9207_ID) && !defined(AD9209_ID)
@@ -102,24 +100,27 @@ uint64_t clk_hz[][4] = {
//#define if_freq 10e6
uint8_t tx_dac_chan_xbar[][4] = { /* dac0, dac1, dac2, dac3 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc13*/
// { AD9081_DAC_CH_0, AD9081_DAC_CH_1 }, /* uc13*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 },
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 },
};
int64_t tx_main_shift[][4] = { /* dac0, dac1, dac2, dac3 */
{ tx_if_freq, tx_if_freq, tx_if_freq, tx_if_freq }, /* uc13*/
{ tx_if_freq, tx_if_freq, tx_if_freq, tx_if_freq }, /* uc13*/
};
int64_t tx_chan_shift[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
int8_t tx_chan_gain[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
uint8_t tx_interp[][2] = {
/* {main DUC Interpolation, Channelizer DUC Interpolation} */
{ 12, 1 }, /* uc13*/
// { 8, 1 }, /* uc13*/
{ 12, 1 }, /* uc13*/
};
#endif
@@ -132,7 +133,7 @@ uint8_t tx_interp[][2] = {
*/
uint8_t rx_cddc_select[] = {
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
// AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1, /* uc13*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
};
/* RX Main Path DDC NCO Frequency Configuration
@@ -146,6 +147,7 @@ uint8_t rx_cddc_select[] = {
int64_t rx_cddc_shift[][4] = {
/* {cddc0, cddc1, cddc2, cddc3 }*/
{ rx_if_freq, rx_if_freq, rx_if_freq, rx_if_freq}, /* uc13*/
{ rx_if_freq, rx_if_freq, rx_if_freq, rx_if_freq}, /* uc13*/
};
/* RX Main Path DDC Data Decimation
* List the ADC_Coarse DDCs desired data decimation
@@ -159,7 +161,7 @@ int64_t rx_cddc_shift[][4] = {
uint8_t rx_cddc_dcm[][4] = {
/*{cddc0, cddc1, cddc2, cddc3} */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
// { AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
};
/* RX Main Path DDC Has Optional Complex to Real Convertor
* rx_cddc_c2r sets the enable for Complex to Real Converter per Main/Coarse DDC
@@ -173,6 +175,7 @@ uint8_t rx_cddc_dcm[][4] = {
*/
uint8_t rx_cddc_c2r[][4] = { /* cddc0, cddc1, cddc2, cddc3 */
{ 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0 }, /* uc13*/
};
/* RX Channelizer/Fine DDC Datapath Selection
* List the ADC Fine DDCs data path for routing Data from Main/ Coarse DDC Datapth to the JESD Tx
@@ -189,7 +192,7 @@ uint8_t rx_cddc_c2r[][4] = { /* cddc0, cddc1, cddc2, cddc3 */
*/
uint8_t rx_fddc_select[] = {
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
// AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc13*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
};
/* RX Channelizer Path DDC NCO Frequency Configuration
* List the ADC_Fine DDCs desired Frequency Shift
@@ -202,6 +205,7 @@ uint8_t rx_fddc_select[] = {
int64_t rx_fddc_shift[][8] = {
/* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
/* RX Channelizer Data Decimation
* List the ADC Fine DDCs desired data decimation
@@ -215,7 +219,7 @@ int64_t rx_fddc_shift[][8] = {
*/
uint8_t rx_fddc_dcm[][8] = { /* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
// { AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
};
uint8_t rx_fddc_c2r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* uc */
@@ -238,7 +242,7 @@ uint8_t rx_fddc_c2r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* uc */
*/
adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2] = {
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
// { { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc13.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
};
/* Total Decimation Settings */
@@ -255,19 +259,17 @@ adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2] = {
*/
uint8_t jtx_chip_dcm[][2] = {
{ 4 }, /* uc13.link0 */
// { 4 }, /* uc13.link0 */
{ 4 }, /* uc13.link0 */
};
uint8_t jtx_logiclane_mapping_pe_brd[2][8] = { { 0, 1, 2, 3, 4, 5, 6, 7 }, { 4, 5, 6, 7, 0, 1, 2, 3 } };
uint8_t jtx_logiclane_mapping_ce_brd[2][8] = { { 6, 4, 3, 2, 1, 0, 7, 5 }, { 2, 0, 7, 7, 7, 7, 3, 1 } };
adi_cms_jesd_param_t jrx_param[] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 15 }, /* uc13: txmode = 378 */
// { 8, 1, 4, 1, 0, 256, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 17 }, /* uc13: txmode = 378 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 15 }, /* uc13: txmode = 378 */
};
adi_cms_jesd_param_t jtx_param[][2] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode C2R ModeS */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16, 0, 0 } }, /* uc13: rxmode = 227, link0 */
// { { 8, 1, 4, 1, 0, 256, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 18, 0, 0 } }, /* uc13: rxmode = 227, link0 */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16, 0, 0 } }, /* uc13: rxmode = 227, link0 */
};

38879
vitis/radar_system/_ide/flash/radar.elf.srec
View File

File diff suppressed because it is too large Load Diff

5
vitis/radar_system/_ide/scripts/ibert.tcl
View File

@@ -10,11 +10,14 @@
# source /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar_system/_ide/scripts/ibert.tcl
#
connect -url tcp:127.0.0.1:3121
targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && level==0 && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-13822093-0"}
fpga -file /home/bkiedinger/projects/castelion/radar_alinx_kintex_ibert/radar_alinx_kintex.runs/impl_1/top.bit
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
loadhw -hw /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/hw/top.xsa -regs
configparams mdm-detect-bscan-mask 2
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
rst -processor
rst -system
after 3000
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
dow /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar/Debug/radar.elf
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }