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bkiedinger@gmail.com
2025-05-20 20:33:12 -05:00
parent 8a1a6ea770
commit fcb291590b
104 changed files with 63299 additions and 45045 deletions
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57
radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.v
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@@ -9,7 +9,9 @@ module digital_rx_chain #
parameter START_SAMPLE_REG_ADDR = 32'h00000008,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 32
parameter integer AXI_DATA_WIDTH = 32,
parameter integer JESD_DATA_WIDTH = 64
// parameter integer JESD_DATA_WIDTH = 32
)
(
input wire clk,
@@ -21,8 +23,8 @@ module digital_rx_chain #
// Input Data
input wire in_tvalid,
input wire [63:0] in_tdata_i,
input wire [63:0] in_tdata_q,
input wire [JESD_DATA_WIDTH-1:0] in_tdata_i,
input wire [JESD_DATA_WIDTH-1:0] in_tdata_q,
// Output Data
axi4s_intf.master rx_out
@@ -38,8 +40,8 @@ wire out_tstart_r;
// ------------------------------
reg in_tstart_reg;
reg in_tvalid_reg;
reg [63:0] in_tdata_i_reg;
reg [63:0] in_tdata_q_reg;
reg [JESD_DATA_WIDTH-1:0] in_tdata_i_reg;
reg [JESD_DATA_WIDTH-1:0] in_tdata_q_reg;
always @ (posedge clk) begin
in_tstart_reg <= start_of_pulse;
in_tvalid_reg <= in_tvalid;
@@ -212,7 +214,6 @@ always @ (posedge clk) begin
pulse_active_fed <= ~pulse_active && pulse_active_q;
pulse_active_fed_q <= pulse_active_fed;
// if (in_tstart_reg && in_tvalid_reg) begin
if (delay_active_fed && in_tvalid_reg) begin
sample_cnt <= 0;
pulse_active <= 1;
@@ -236,7 +237,7 @@ assign out_tvalid_r = in_tvalid_reg && (pulse_active || delay_active_fed);
// Buffer
// ------------------------------
axi4s_intf # (
.AXI_DATA_WIDTH(128),
.AXI_DATA_WIDTH(JESD_DATA_WIDTH * 2),
.AXI_USER_WIDTH(1)
)
axis_odec_out (
@@ -245,7 +246,7 @@ axi4s_intf # (
);
axi4s_intf # (
.AXI_DATA_WIDTH(128),
.AXI_DATA_WIDTH(JESD_DATA_WIDTH * 2),
.AXI_USER_WIDTH(1)
)
axis_pulse_buffer_out (
@@ -266,6 +267,7 @@ assign axis_odec_out.tvalid = out_tvalid_r && (pulse_active || delay_active_fed)
assign axis_odec_out.tlast = out_tlast_r;
assign axis_odec_out.tuser = out_tstart_r;
//204C
assign axis_odec_out.tdata[15:0] = in_tdata_i_reg[63:48];
assign axis_odec_out.tdata[31:16] = in_tdata_q_reg[63:48];
assign axis_odec_out.tdata[47:32] = in_tdata_i_reg[47:32];
@@ -275,18 +277,6 @@ assign axis_odec_out.tdata[95:80] = in_tdata_q_reg[31:16];
assign axis_odec_out.tdata[111:96] = in_tdata_i_reg[15:0];
assign axis_odec_out.tdata[127:112] = in_tdata_q_reg[15:0];
//assign axis_odec_out.tdata[15:0] = in_tdata_i_reg[15:0];
//assign axis_odec_out.tdata[31:16] = in_tdata_q_reg[15:0];
//assign axis_odec_out.tdata[47:32] = in_tdata_i_reg[31:16];
//assign axis_odec_out.tdata[63:48] = in_tdata_q_reg[31:16];
//assign axis_odec_out.tdata[79:64] = in_tdata_i_reg[47:32];
//assign axis_odec_out.tdata[95:80] = in_tdata_q_reg[47:32];
//assign axis_odec_out.tdata[111:96] = in_tdata_i_reg[63:48];
//assign axis_odec_out.tdata[127:112] = in_tdata_q_reg[63:48];
// assign axis_odec_out.tdata[63:0] = in_tdata_i_reg[63:0];
// assign axis_odec_out.tdata[127:64] = in_tdata_q_reg[63:0];
pulse_buffer_fifo pulse_buffer_fifo_i (
.s_axis_aresetn(~reset),
.s_axis_aclk(clk),
@@ -345,8 +335,33 @@ dig_rx_clock_converter dig_rx_clock_converter_i (
.m_axis_tuser(rx_out.tuser)
);
//204B
//assign axis_odec_out.tdata[15:0] = in_tdata_i_reg[31:16];
//assign axis_odec_out.tdata[31:16] = in_tdata_q_reg[31:16];
//assign axis_odec_out.tdata[47:32] = in_tdata_i_reg[15:0];
//assign axis_odec_out.tdata[63:48] = in_tdata_q_reg[15:0];
//pulse_buffer_204B_fifo pulse_buffer_fifo_i (
// .s_axis_aresetn(~reset),
// .s_axis_aclk(clk),
// .s_axis_tvalid(axis_odec_out.tvalid),
// .s_axis_tready(),
// .s_axis_tdata(axis_odec_out.tdata),
// .s_axis_tlast(axis_odec_out.tlast),
// .s_axis_tuser(axis_odec_out.tuser),
// .m_axis_aclk(rx_out.clk),
// .m_axis_tvalid(rx_out.tvalid),
// .m_axis_tready(rx_out.tready),
// .m_axis_tdata(rx_out.tdata),
// .m_axis_tlast(rx_out.tlast),
// .m_axis_tuser(rx_out.tuser)
//);
assign rx_out.tkeep = '1;
// assign rx_out.tuser = reg_num_samples;
assign rx_out.tdest = 1;
endmodule

93
radar_alinx_kintex.srcs/sources_1/hdl/top.v
View File

@@ -115,8 +115,16 @@ module top #
input wire jesd_sysref_p,
input wire jesd_sysref_n,
input wire jesd_sync_in_p,
input wire jesd_sync_in_n,
output wire jesd_sync_out_p,
output wire jesd_sync_out_n,
input wire jesd_core_clk_p,
input wire jesd_core_clk_n,
// input wire jesd_core_clk2_p,
// input wire jesd_core_clk2_n,
input wire jesd_qpll0_refclk_p,
input wire jesd_qpll0_refclk_n,
@@ -168,20 +176,26 @@ module top #
wire jesd_axis_rx_cmd_tready;
wire [7:0]jesd_axis_rx_cmd_tuser;
wire jesd_axis_rx_cmd_tvalid;
wire [511:0]jesd_axis_rx_tdata;
wire jesd_axis_rx_tvalid;
wire [255:0]jesd_axis_tx_cmd_tdata;
wire jesd_axis_tx_cmd_tready;
wire jesd_axis_tx_cmd_tvalid;
wire [511:0]jesd_axis_tx_tdata;
wire jesd_axis_tx_tready;
// 204C
wire [511:0]jesd_axis_tx_tdata;
wire [511:0]jesd_axis_rx_tdata;
//204B
// wire [255:0]jesd_axis_tx_tdata;
// wire [255:0]jesd_axis_rx_tdata;
wire jesd_rx_core_reset;
wire jesd_rx_sys_reset;
wire jesd_tx_core_reset;
wire jesd_tx_sys_reset;
wire jesd_core_clk;
wire jesd_core_clk_in;
wire jesd_core_clk2_in;
wire [14:0] dac0_wf_bram_addr;
wire dac0_wf_bram_clk;
@@ -234,10 +248,55 @@ module top #
.O (jesd_core_clk_in)
);
// IBUFDS #(
// .DIFF_TERM("TRUE"), // Differential Termination
// .IBUF_LOW_PWR("FALSE"), // Low power="TRUE", Highest performance="FALSE"
// .IOSTANDARD("LVDS") // Specify the input I/O standard
// ) core_clk2_ibufds_c (
// .I (jesd_core_clk2_p),
// .IB (jesd_core_clk2_n),
// .O (jesd_core_clk2_in)
// );
BUFG BUFG_inst (
.O(jesd_core_clk),
.I(jesd_core_clk_in)
);
);
wire jesd_core_clk_locked;
// jesd_core_clk_wiz jesd_core_clk_wiz
// (
// .clk_out1(jesd_core_clk),
//// .clk_in_sel(jesd_clk_sel),
// .locked(jesd_core_clk_locked),
//// .clk_in1_p(jesd_core_clk_p),
//// .clk_in1_n(jesd_core_clk_n),
//// .clk_in2_p(jesd_core_clk2_p),
//// .clk_in2_n(jesd_core_clk2_n)
// .clk_in1(jesd_core_clk_in)
//// .clk_in2(jesd_core_clk2_in)
// );
wire jesd_sync_in;
IBUFDS #(
.DIFF_TERM("TRUE"), // Differential Termination
.IBUF_LOW_PWR("FALSE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("LVDS") // Specify the input I/O standard
) jesd_sync_in_ibufds (
.I (jesd_sync_in_p),
.IB (jesd_sync_in_n),
.O (jesd_sync_in)
);
wire jesd_sync_out;
OBUFDS jesd_sync_out_ibufds (
.O (jesd_sync_out_p),
.OB (jesd_sync_out_n),
.I (jesd_sync_out)
);
IOBUF mdio_mdio_iobuf
(.I(mdio_mdio_o),
@@ -579,15 +638,8 @@ module top #
.common1_qpll1_lock_out(common1_qpll1_lock_out),
.jesd_axis_tx_aresetn(jesd_axis_tx_aresetn),
.jesd_axis_rx_aresetn(jesd_axis_rx_aresetn),
.jesd_axis_rx_cmd_tdata(jesd_axis_rx_cmd_tdata),
.jesd_axis_rx_cmd_tready(jesd_axis_rx_cmd_tready),
.jesd_axis_rx_cmd_tuser(jesd_axis_rx_cmd_tuser),
.jesd_axis_rx_cmd_tvalid(jesd_axis_rx_cmd_tvalid),
.jesd_axis_rx_tdata(jesd_axis_rx_tdata),
.jesd_axis_rx_tvalid(jesd_axis_rx_tvalid),
.jesd_axis_tx_cmd_tdata(jesd_axis_tx_cmd_tdata),
.jesd_axis_tx_cmd_tready(jesd_axis_tx_cmd_tready),
.jesd_axis_tx_cmd_tvalid(jesd_axis_tx_cmd_tvalid),
.jesd_axis_tx_tdata(jesd_axis_tx_tdata),
.jesd_axis_tx_tready(jesd_axis_tx_tready),
.jesd_qpll0_refclk_clk_n(jesd_qpll0_refclk_n),
@@ -604,6 +656,17 @@ module top #
.jesd_rx_sys_reset(jesd_rx_sys_reset),
.jesd_core_clk(jesd_core_clk),
.jesd_axis_rx_cmd_tdata(jesd_axis_rx_cmd_tdata),
.jesd_axis_rx_cmd_tready(jesd_axis_rx_cmd_tready),
.jesd_axis_rx_cmd_tuser(jesd_axis_rx_cmd_tuser),
.jesd_axis_rx_cmd_tvalid(jesd_axis_rx_cmd_tvalid),
.jesd_axis_tx_cmd_tdata(jesd_axis_tx_cmd_tdata),
.jesd_axis_tx_cmd_tready(jesd_axis_tx_cmd_tready),
.jesd_axis_tx_cmd_tvalid(jesd_axis_tx_cmd_tvalid),
// .jesd_tx_sync(jesd_sync_in),
// .jesd_rx_sync(jesd_sync_out),
.eth_clk(eth_clk[0]),
.eth_resetn(eth_resetn[0]),
.udp_rx_tdata(rx_udp_axis[0].tdata),
@@ -661,7 +724,9 @@ module top #
wire eth_reset;
assign leds = gpo[3:0];
assign leds[1:0] = gpo[1:0];
assign leds[2] = 0;
assign leds[3] = jesd_core_clk_locked;
assign fmc_power_en = gpo[4];
assign resetb = gpo[5];
assign jesd_rx_core_reset = gpo[6];
@@ -669,11 +734,13 @@ module top #
assign jesd_rx_sys_reset = gpo[8];
assign jesd_tx_sys_reset = gpo[9];
assign qspi_flash_aresetn = ~gpo[10];
assign jesd_clk_sel = gpo[11];
assign eth_reset = gpo[15];
assign gpi[31:3] = 0;
assign gpi[31:4] = 0;
// assign gpi[31] = start_of_cpi;
// assign gpi[30] = start_of_pulse;
assign gpi[3] = jesd_core_clk_locked;
assign gpi[2] = common1_qpll1_lock_out;
assign gpi[1] = common0_qpll1_lock_out;
assign gpi[0] = ddr_init_calib_complete;
@@ -806,6 +873,8 @@ module top #
.in_tvalid(jesd_axis_rx_tvalid),
.in_tdata_i(jesd_axis_rx_tdata[i*128+63 :i*128+0]),
.in_tdata_q(jesd_axis_rx_tdata[i*128+127 :i*128+64]),
// .in_tdata_i(jesd_axis_rx_tdata[i*64+31 :i*64+0]),
// .in_tdata_q(jesd_axis_rx_tdata[i*64+63 :i*64+32]),
.rx_out(rx_axis[i])
);

83
radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.v
View File

@@ -53,6 +53,7 @@ module waveform_gen #
output wire [511:0] jesd_tx
// output wire [255:0] jesd_tx
);
@@ -179,6 +180,9 @@ reg delay_active_fed;
reg [255:0] jesd_out_reg;
reg [255:0] all_brams_out;
//reg [127:0] jesd_out_reg;
//reg [127:0] all_brams_out;
always @ (posedge clk) begin
if (reset == 1'b1) begin
@@ -248,24 +252,12 @@ always @ (posedge clk) begin
end
//assign all_brams_out[16*0+15 + 384 : 16*0 + 384] = dac3_bram_dout[16*6+15:16*6];
//assign all_brams_out[16*1+15 + 384 : 16*1 + 384] = dac3_bram_dout[16*4+15:16*4];
//assign all_brams_out[16*2+15 + 384 : 16*2 + 384] = dac3_bram_dout[16*2+15:16*2];
//assign all_brams_out[16*3+15 + 384 : 16*3 + 384] = dac3_bram_dout[16*0+15:16*0];
//assign all_brams_out[16*4+15 + 384 : 16*4 + 384] = dac3_bram_dout[16*7+15:16*7];
//assign all_brams_out[16*5+15 + 384 : 16*5 + 384] = dac3_bram_dout[16*5+15:16*5];
//assign all_brams_out[16*6+15 + 384 : 16*6 + 384] = dac3_bram_dout[16*3+15:16*3];
//assign all_brams_out[16*7+15 + 384 : 16*7 + 384] = dac3_bram_dout[16*1+15:16*1];
//assign all_brams_out[16*0+15 + 256 : 16*0 + 256] = dac2_bram_dout[16*6+15:16*6];
//assign all_brams_out[16*1+15 + 256 : 16*1 + 256] = dac2_bram_dout[16*4+15:16*4];
//assign all_brams_out[16*2+15 + 256 : 16*2 + 256] = dac2_bram_dout[16*2+15:16*2];
//assign all_brams_out[16*3+15 + 256 : 16*3 + 256] = dac2_bram_dout[16*0+15:16*0];
//assign all_brams_out[16*4+15 + 256 : 16*4 + 256] = dac2_bram_dout[16*7+15:16*7];
//assign all_brams_out[16*5+15 + 256 : 16*5 + 256] = dac2_bram_dout[16*5+15:16*5];
//assign all_brams_out[16*6+15 + 256 : 16*6 + 256] = dac2_bram_dout[16*3+15:16*3];
//assign all_brams_out[16*7+15 + 256 : 16*7 + 256] = dac2_bram_dout[16*1+15:16*1];
assign dac1_bram_addr = dac0_bram_addr;
// 204C
// remap data for easier software loading of BRAMs
assign all_brams_out[16*0+15 + 128 : 16*0 + 128] = dac1_bram_dout[16*6+15:16*6];
assign all_brams_out[16*1+15 + 128 : 16*1 + 128] = dac1_bram_dout[16*4+15:16*4];
assign all_brams_out[16*2+15 + 128 : 16*2 + 128] = dac1_bram_dout[16*2+15:16*2];
@@ -284,11 +276,6 @@ assign all_brams_out[16*5+15 + 0 : 16*5 + 0] = dac0_bram_dout[16*5+15:16*5
assign all_brams_out[16*6+15 + 0 : 16*6 + 0] = dac0_bram_dout[16*3+15:16*3];
assign all_brams_out[16*7+15 + 0 : 16*7 + 0] = dac0_bram_dout[16*1+15:16*1];
assign dac1_bram_addr = dac0_bram_addr;
//assign dac2_bram_addr = dac0_bram_addr;
//assign dac3_bram_addr = dac0_bram_addr;
// dac2 and dac3 are used for LOs, so just need a constant 1 + j0 output. The NCO
// inside the AD9081 will be used to turn this into a tone
@@ -296,6 +283,23 @@ assign jesd_tx[511:384] = {16'h0000, 16'h0000, 16'h0000, 16'h0000, 16'h7FFF, 16'
assign jesd_tx[383:256] = {16'h0000, 16'h0000, 16'h0000, 16'h0000, 16'h7FFF, 16'h7FFF, 16'h7FFF, 16'h7FFF};
assign jesd_tx[255:0] = jesd_out_reg;
//204B
//assign all_brams_out[16*0+15 + 64 : 16*0 + 64] = dac1_bram_dout[16*2+15:16*2];
//assign all_brams_out[16*1+15 + 64 : 16*1 + 64] = dac1_bram_dout[16*0+15:16*0];
//assign all_brams_out[16*2+15 + 64 : 16*2 + 64] = dac1_bram_dout[16*3+15:16*3];
//assign all_brams_out[16*3+15 + 64 : 16*3 + 64] = dac1_bram_dout[16*1+15:16*1];
//assign all_brams_out[16*0+15 + 0 : 16*0 + 0] = dac0_bram_dout[16*2+15:16*2];
//assign all_brams_out[16*1+15 + 0 : 16*1 + 0] = dac0_bram_dout[16*0+15:16*0];
//assign all_brams_out[16*2+15 + 0 : 16*2 + 0] = dac0_bram_dout[16*3+15:16*3];
//assign all_brams_out[16*3+15 + 0 : 16*3 + 0] = dac0_bram_dout[16*1+15:16*1];
//assign jesd_tx[255:192] = {16'h0000, 16'h0000, 16'h7FFF, 16'h7FFF};
//assign jesd_tx[191:128] = {16'h0000, 16'h0000, 16'h7FFF, 16'h7FFF};
//assign jesd_tx[127:0] = jesd_out_reg;
wf_memory dac0_wf_mem (
.clka(dac0_wf_bram_clk),
.ena(dac0_wf_bram_en),
@@ -327,38 +331,7 @@ wf_memory dac1_wf_mem (
.dinb(0),
.doutb(dac1_bram_dout)
);
//wf_memory dac2_wf_mem (
// .clka(dac2_wf_bram_clk),
// .ena(dac2_wf_bram_en),
// .wea(dac2_wf_bram_we),
// .addra(dac2_wf_bram_addr[14:2]),
// .dina(dac2_wf_bram_din),
// .douta(dac2_wf_bram_dout),
// .clkb(clk),
// .enb(1'b1),
// .web(1'b0),
// .addrb(dac2_bram_addr),
// .dinb(0),
// .doutb(dac2_bram_dout)
//);
//wf_memory dac3_wf_mem (
// .clka(dac3_wf_bram_clk),
// .ena(dac3_wf_bram_en),
// .wea(dac3_wf_bram_we),
// .addra(dac3_wf_bram_addr[14:2]),
// .dina(dac3_wf_bram_din),
// .douta(dac3_wf_bram_dout),
// .clkb(clk),
// .enb(1'b1),
// .web(1'b0),
// .addrb(dac3_bram_addr),
// .dinb(0),
// .doutb(dac3_bram_dout)
//);
endmodule