bkiedinger/castelion_radar_alinx_kintex
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This commit is contained in:
bkiedinger@gmail.com
2025-05-20 20:33:12 -05:00
parent 8a1a6ea770
commit fcb291590b
104 changed files with 63299 additions and 45045 deletions
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radar_alinx_kintex.xpr
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@@ -7,7 +7,7 @@
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="c179ea77804d47eabf9d7773e858daa9"/>
<Option Name="Part" Val="xcku040-ffva1156-1-c"/>
<Option Name="Part" Val="xcku040-ffva1156-2-i"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
@@ -63,13 +63,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="31"/>
<Option Name="WTModelSimExportSim" Val="31"/>
<Option Name="WTQuestaExportSim" Val="31"/>
<Option Name="WTXSimExportSim" Val="47"/>
<Option Name="WTModelSimExportSim" Val="47"/>
<Option Name="WTQuestaExportSim" Val="47"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="31"/>
<Option Name="WTRivieraExportSim" Val="31"/>
<Option Name="WTActivehdlExportSim" Val="31"/>
<Option Name="WTVcsExportSim" Val="47"/>
<Option Name="WTRivieraExportSim" Val="47"/>
<Option Name="WTActivehdlExportSim" Val="47"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -568,20 +568,6 @@
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="microblaze_bd" Type="BlockSrcs" RelSrcDir="$PSRCDIR/microblaze_bd" RelGenDir="$PGENDIR/microblaze_bd">
<File Path="$PSRCDIR/sources_1/bd/microblaze_bd/microblaze_bd.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="microblaze_bd"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="axis_switch_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axis_switch_0" RelGenDir="$PGENDIR/axis_switch_0">
<File Path="$PSRCDIR/sources_1/ip/axis_switch_0/axis_switch_0.xci">
<FileInfo>
@@ -708,6 +694,50 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pulse_buffer_204B_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pulse_buffer_204B_fifo" RelGenDir="$PGENDIR/pulse_buffer_204B_fifo">
<File Path="$PSRCDIR/sources_1/ip/pulse_buffer_204B_fifo/pulse_buffer_204B_fifo.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="pulse_buffer_204B_fifo"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="microblaze_bd" Type="BlockSrcs" RelSrcDir="$PSRCDIR/microblaze_bd" RelGenDir="$PGENDIR/microblaze_bd">
<File Path="$PSRCDIR/sources_1/bd/microblaze_bd/microblaze_bd.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="microblaze_bd"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="jesd_core_clk_wiz" Type="BlockSrcs" RelSrcDir="$PSRCDIR/jesd_core_clk_wiz" RelGenDir="$PGENDIR/jesd_core_clk_wiz">
<File Path="$PSRCDIR/sources_1/ip/jesd_core_clk_wiz/jesd_core_clk_wiz.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="jesd_core_clk_wiz"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@@ -731,7 +761,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="19">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-1-c" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -741,7 +771,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="microblaze_bd_synth_1" Type="Ft3:Synth" SrcSet="microblaze_bd" Part="xcku040-ffva1156-1-c" ConstrsSet="microblaze_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/microblaze_bd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1">
<Run Id="axis_switch_0_synth_1" Type="Ft3:Synth" SrcSet="axis_switch_0" Part="xcku040-ffva1156-2-i" ConstrsSet="axis_switch_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axis_switch_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -751,7 +781,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axis_switch_0_synth_1" Type="Ft3:Synth" SrcSet="axis_switch_0" Part="xcku040-ffva1156-1-c" ConstrsSet="axis_switch_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axis_switch_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1">
<Run Id="hdr_mem_synth_1" Type="Ft3:Synth" SrcSet="hdr_mem" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_mem" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_mem_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -761,7 +791,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_mem_synth_1" Type="Ft3:Synth" SrcSet="hdr_mem" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_mem" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_mem_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1">
<Run Id="dig_rx_clock_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_clock_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_clock_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_clock_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -771,7 +801,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_clock_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_clock_converter" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_clock_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_clock_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1">
<Run Id="dig_rx_dwidth_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_dwidth_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_dwidth_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_dwidth_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -781,7 +811,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_dwidth_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_dwidth_converter" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_dwidth_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_dwidth_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1">
<Run Id="pulse_buffer_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pulse_buffer_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -791,7 +821,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pulse_buffer_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_fifo" Part="xcku040-ffva1156-1-c" ConstrsSet="pulse_buffer_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pulse_buffer_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1">
<Run Id="eth_xcvr_gt_channel_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_channel" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_channel" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_channel_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -801,7 +831,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_channel_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_channel" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_channel" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_channel_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1">
<Run Id="eth_xcvr_gt_full_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_full" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_full" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_full_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -811,7 +841,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_full_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_full" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_full" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_full_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1">
<Run Id="wf_memory_synth_1" Type="Ft3:Synth" SrcSet="wf_memory" Part="xcku040-ffva1156-2-i" ConstrsSet="wf_memory" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/wf_memory_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -821,7 +851,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="wf_memory_synth_1" Type="Ft3:Synth" SrcSet="wf_memory" Part="xcku040-ffva1156-1-c" ConstrsSet="wf_memory" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/wf_memory_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1">
<Run Id="hdr_fifo_synth_1" Type="Ft3:Synth" SrcSet="hdr_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -831,7 +861,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_fifo_synth_1" Type="Ft3:Synth" SrcSet="hdr_fifo" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1">
<Run Id="pulse_buffer_204B_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_204B_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_204B_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pulse_buffer_204B_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_204B_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_204B_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -841,7 +871,27 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="microblaze_bd_synth_1" Type="Ft3:Synth" SrcSet="microblaze_bd" Part="xcku040-ffva1156-2-i" ConstrsSet="microblaze_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/microblaze_bd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="jesd_core_clk_wiz_synth_1" Type="Ft3:Synth" SrcSet="jesd_core_clk_wiz" Part="xcku040-ffva1156-2-i" ConstrsSet="jesd_core_clk_wiz" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/jesd_core_clk_wiz_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/jesd_core_clk_wiz_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/jesd_core_clk_wiz_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -859,7 +909,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="microblaze_bd_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="microblaze_bd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="microblaze_bd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_impl_1">
<Run Id="axis_switch_0_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="axis_switch_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axis_switch_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -876,7 +926,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axis_switch_0_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="axis_switch_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axis_switch_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1">
<Run Id="hdr_mem_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_mem" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_mem_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -893,7 +943,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_mem_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_mem" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_mem_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1">
<Run Id="dig_rx_clock_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_clock_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_clock_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -910,7 +960,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_clock_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_clock_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_clock_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1">
<Run Id="dig_rx_dwidth_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_dwidth_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_dwidth_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -927,7 +977,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_dwidth_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_dwidth_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_dwidth_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1">
<Run Id="pulse_buffer_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pulse_buffer_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -944,7 +994,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pulse_buffer_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="pulse_buffer_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pulse_buffer_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1">
<Run Id="eth_xcvr_gt_channel_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_channel" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_channel_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -961,7 +1011,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_channel_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_channel" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_channel_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1">
<Run Id="eth_xcvr_gt_full_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_full" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_full_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -978,7 +1028,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<Run Id="eth_xcvr_gt_full_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_full" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_full_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1">
<Run Id="wf_memory_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="wf_memory" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="wf_memory_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -995,7 +1045,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="wf_memory_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="wf_memory" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="wf_memory_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1">
<Run Id="hdr_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1012,7 +1062,41 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_impl_1">
<Run Id="pulse_buffer_204B_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_204B_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pulse_buffer_204B_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_204B_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_204B_fifo_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="microblaze_bd_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="microblaze_bd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="microblaze_bd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="jesd_core_clk_wiz_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="jesd_core_clk_wiz" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="jesd_core_clk_wiz_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/jesd_core_clk_wiz_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/jesd_core_clk_wiz_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1030,6 +1114,62 @@
<RQSFiles/>
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<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1306]"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1271]"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="NewSeverity" Val="ANY"/>
<MsgAttr Name="Id" Val="[BD 41-1306]"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="NewSeverity" Val="ANY"/>
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