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This commit is contained in:
bkiedinger@gmail.com
2025-05-20 20:33:12 -05:00
parent 8a1a6ea770
commit fcb291590b
104 changed files with 63299 additions and 45045 deletions
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48
vitis/radar/_ide/bitstream/top.mmi
View File

@@ -13,49 +13,49 @@
<AddressSpace Name="microblaze_bd_i_microblaze_0.microblaze_bd_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="32767">
<AddressSpaceRange Name="microblaze_bd_i_microblaze_0.microblaze_bd_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="32767" CoreMemory_Width="0" MemoryType="RAM_SP" MemoryConfiguration="">
<BusBlock>
<BitLane MemType="RAMB36" Placement="X6Y46" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y9" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="7" LSB="4"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X5Y44" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y10" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="3" LSB="0"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y44" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y14" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="15" LSB="12"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y43" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y13" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="11" LSB="8"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X5Y46" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y6" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="23" LSB="20"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X5Y45" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y5" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="19" LSB="16"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y45" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y11" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="31" LSB="28"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y41" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X6Y7" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="27" LSB="24"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
@@ -69,97 +69,97 @@
<AddressSpace Name="microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_microblaze_I.microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_dlmb_cntlr" Begin="0" End="65535">
<AddressSpaceRange Name="microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_microblaze_I.microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_dlmb_cntlr" Begin="0" End="65535" CoreMemory_Width="0" MemoryType="RAM_SP" MemoryConfiguration="">
<BusBlock>
<BitLane MemType="RAMB36" Placement="X0Y9" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X2Y24" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="7" LSB="6"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y7" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X2Y25" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="5" LSB="4"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y11" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y24" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="3" LSB="2"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y14" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y22" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="1" LSB="0"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y6" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X0Y25" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="15" LSB="14"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y5" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X0Y24" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="13" LSB="12"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y7" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y26" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="11" LSB="10"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y6" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y25" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="9" LSB="8"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y13" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y19" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="23" LSB="22"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X2Y13" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X2Y19" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="21" LSB="20"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X2Y10" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y17" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="19" LSB="18"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X2Y9" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X0Y20" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="17" LSB="16"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y13" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X2Y21" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="31" LSB="30"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X2Y12" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X0Y18" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="29" LSB="28"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y14" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X0Y22" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="27" LSB="26"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X2Y11" Read_Width="0" SLR_INDEX="-1">
<BitLane MemType="RAMB36" Placement="X1Y18" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="25" LSB="24"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>

2
vitis/radar/_ide/hwspec.checksum
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@@ -1 +1 @@
2759812199
2843589716

2
vitis/radar/_ide/launch/Debugger_radar-Default.launch
View File

@@ -16,7 +16,7 @@
<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.bit.file" value="/home/bkiedinger/projects/castelion/radar_alinx_kintex/radar_alinx_kintex.runs/impl_1/top.bit"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.init.tcl" value=""/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uipl.powerup" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{&quot;microblaze_0&quot;:{&quot;xilinx.tcf.application&quot;:&quot;Debug/radar.elf&quot;,&quot;xilinx.tcf.datafiles&quot;:&quot;&quot;,&quot;xilinx.tcf.no_download&quot;:false,&quot;xilinx.tcf.profile_enabled&quot;:false,&quot;xilinx.tcf.profile_frequency&quot;:&quot;10000&quot;,&quot;xilinx.tcf.profile_non_int_frequency&quot;:&quot;150000000&quot;,&quot;xilinx.tcf.profile_non_int_high_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_low_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_use_count_instr&quot;:false,&quot;xilinx.tcf.profile_non_int_use_cumulate&quot;:false,&quot;xilinx.tcf.profile_non_intrusive_support&quot;:false,&quot;xilinx.tcf.profile_store_address&quot;:&quot;0x0&quot;,&quot;xilinx.tcf.profile_use_intrusive&quot;:false,&quot;xilinx.tcf.project&quot;:&quot;radar&quot;,&quot;xilinx.tcf.relocate&quot;:false,&quot;xilinx.tcf.relocate_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.reset&quot;:true,&quot;xilinx.tcf.stop_at_entry&quot;:false}}"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{&quot;microblaze_0&quot;:{&quot;xilinx.tcf.application&quot;:&quot;Debug/radar.elf&quot;,&quot;xilinx.tcf.datafiles&quot;:&quot;&quot;,&quot;xilinx.tcf.no_download&quot;:false,&quot;xilinx.tcf.profile_enabled&quot;:false,&quot;xilinx.tcf.profile_frequency&quot;:&quot;10000&quot;,&quot;xilinx.tcf.profile_non_int_frequency&quot;:&quot;125000000&quot;,&quot;xilinx.tcf.profile_non_int_high_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_low_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_use_count_instr&quot;:false,&quot;xilinx.tcf.profile_non_int_use_cumulate&quot;:false,&quot;xilinx.tcf.profile_non_intrusive_support&quot;:false,&quot;xilinx.tcf.profile_store_address&quot;:&quot;0x0&quot;,&quot;xilinx.tcf.profile_use_intrusive&quot;:false,&quot;xilinx.tcf.project&quot;:&quot;radar&quot;,&quot;xilinx.tcf.relocate&quot;:false,&quot;xilinx.tcf.relocate_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.reset&quot;:true,&quot;xilinx.tcf.stop_at_entry&quot;:false}}"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.selection" value="microblaze_0"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="true"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproject.name" value="radar"/>

2
vitis/radar/_ide/launch/Debugger_radar-sw only.launch
View File

@@ -16,7 +16,7 @@
<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.bit.file" value="/home/bkiedinger/projects/castelion/radar_alinx_kintex/radar_alinx_kintex.runs/impl_1/top.bit"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.init.tcl" value=""/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uipl.powerup" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{&quot;microblaze_0&quot;:{&quot;xilinx.tcf.application&quot;:&quot;Debug/radar.elf&quot;,&quot;xilinx.tcf.datafiles&quot;:&quot;&quot;,&quot;xilinx.tcf.no_download&quot;:false,&quot;xilinx.tcf.profile_enabled&quot;:false,&quot;xilinx.tcf.profile_frequency&quot;:&quot;10000&quot;,&quot;xilinx.tcf.profile_non_int_frequency&quot;:&quot;150000000&quot;,&quot;xilinx.tcf.profile_non_int_high_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_low_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_use_count_instr&quot;:false,&quot;xilinx.tcf.profile_non_int_use_cumulate&quot;:false,&quot;xilinx.tcf.profile_non_intrusive_support&quot;:false,&quot;xilinx.tcf.profile_store_address&quot;:&quot;0x0&quot;,&quot;xilinx.tcf.profile_use_intrusive&quot;:false,&quot;xilinx.tcf.project&quot;:&quot;radar&quot;,&quot;xilinx.tcf.relocate&quot;:false,&quot;xilinx.tcf.relocate_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.reset&quot;:true,&quot;xilinx.tcf.stop_at_entry&quot;:false}}"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{&quot;microblaze_0&quot;:{&quot;xilinx.tcf.application&quot;:&quot;Debug/radar.elf&quot;,&quot;xilinx.tcf.datafiles&quot;:&quot;&quot;,&quot;xilinx.tcf.no_download&quot;:false,&quot;xilinx.tcf.profile_enabled&quot;:false,&quot;xilinx.tcf.profile_frequency&quot;:&quot;10000&quot;,&quot;xilinx.tcf.profile_non_int_frequency&quot;:&quot;125000000&quot;,&quot;xilinx.tcf.profile_non_int_high_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_low_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_use_count_instr&quot;:false,&quot;xilinx.tcf.profile_non_int_use_cumulate&quot;:false,&quot;xilinx.tcf.profile_non_intrusive_support&quot;:false,&quot;xilinx.tcf.profile_store_address&quot;:&quot;0x0&quot;,&quot;xilinx.tcf.profile_use_intrusive&quot;:false,&quot;xilinx.tcf.project&quot;:&quot;radar&quot;,&quot;xilinx.tcf.relocate&quot;:false,&quot;xilinx.tcf.relocate_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.reset&quot;:true,&quot;xilinx.tcf.stop_at_entry&quot;:false}}"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.selection" value="microblaze_0"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproject.name" value="radar"/>

2
vitis/radar/radar.prj
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="8781df679aa71a5344fa22cfacec20c4">
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="31c4a066f121f9dfdf4b2a6e46d178c9">
<configuration name="Debug" id="xilinx.gnu.mb.exe.debug.245787499">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>

1
vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_config.h
View File

@@ -52,6 +52,7 @@
#define AD9081_SERDES_RST_WAIT 50000
#define AD9081_DESER_MODE_204B_BR_TRESH 8000000000ULL
#define AD9081_DESER_MODE_204C_BR_TRESH 16000000000ULL
//#define AD9081_DESER_MODE_204C_BR_TRESH 14000000000ULL
#define AD9081_IL_CTLE_UPPER_DB_THRESH 10
/* var error report */

1
vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_adc.c
View File

@@ -1081,6 +1081,7 @@ int32_t adi_ad9081_adc_ddc_coarse_nco_set(adi_ad9081_device_t *device, uint8_t c
err = adi_ad9081_hal_calc_rx_nco_ftw(device, device->dev_info.adc_freq_hz, cddc_shift_hz, &ftw);
AD9081_ERROR_RETURN(err);
xil_printf("ADC FTW 0x%08x 0x%08x\r\n", (uint32_t)(ftw >> 32), (uint32_t)(ftw & 0xFFFFFFFF));
err = adi_ad9081_adc_ddc_coarse_nco_ftw_set(device, cddcs, ftw, 0, 0);
AD9081_ERROR_RETURN(err);

3
vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_dac.c
View File

@@ -534,6 +534,7 @@ int32_t adi_ad9081_dac_duc_nco_set(adi_ad9081_device_t *device, uint8_t dacs, ui
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_calc_tx_nco_ftw(device, device->dev_info.dac_freq_hz, nco_shift_hz, &ftw);
AD9081_ERROR_RETURN(err);
xil_printf("DAC FTW 0x%08x 0x%08x\r\n", (uint32_t)(ftw >> 32), (uint32_t)(ftw & 0xFFFFFFFF));
err = adi_ad9081_dac_duc_nco_ftw_set(device, dacs, AD9081_DAC_CH_NONE, ftw, 0, 0);
AD9081_ERROR_RETURN(err);
}
@@ -1811,4 +1812,4 @@ int32_t adi_ad9081_dac_run_startup_cal(adi_ad9081_device_t *device, uint8_t dacs
}
return API_CMS_ERROR_OK;
}
/*! @} */
/*! @} */

1
vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_device.c
View File

@@ -665,6 +665,7 @@ int32_t adi_ad9081_device_reg8_access_check(adi_ad9081_device_t *device)
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_TEST_FAILED;
}
err = adi_ad9081_hal_reg_set(device, REG_PAGEINDX_DAC_CHAN_ADDR, reg8);
AD9081_ERROR_RETURN(err);

1
vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_jesd.c
View File

@@ -737,6 +737,7 @@ int32_t adi_ad9081_jesd_rx_ctle_filter_set(adi_ad9081_device_t *device, uint8_t
AD9081_INVALID_PARAM_RETURN(ctle_filter < 1 || ctle_filter > 4) /*Range 1-4 corresponding CTLE cutoff frequency to channel insertion loss*/
err = adi_ad9081_hal_cbusjrx_reg_set(device, 0xfd, (1 << ctle_filter) - 1, lanes); /* @ADDR_CBUS_RX_DFE_CTL55 */
// err = adi_ad9081_hal_cbusjrx_reg_set(device, 0xfd, 0, lanes); /* @ADDR_CBUS_RX_DFE_CTL55 */
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;

5
vitis/radar/src/ad9081_api/adi_inc/adi_ad9081.h
View File

@@ -284,7 +284,8 @@
#define AD9081_ADC_CLK_FREQ_HZ_MAX 4000000000ULL
#define AD9081_REF_CLK_FREQ_HZ_MIN 25000000ULL
#define AD9081_REF_CLK_FREQ_HZ_MAX 3000000000ULL
#define AD9081_JESDRX_204C_CAL_THRESH 16000000000ULL
//#define AD9081_JESDRX_204C_CAL_THRESH 16000000000ULL
#define AD9081_JESDRX_204C_CAL_THRESH 12000000000ULL
#define AD9081_JESD_SER_COUNT 8
#define AD9081_JESD_DESER_COUNT 8
@@ -6049,4 +6050,4 @@ int32_t adi_ad9081_device_cbuspll_register_get(adi_ad9081_device_t *device, uint
#endif
#endif /* __ADI_AD9081_H__ */
/*! @} */
/*! @} */

487
vitis/radar/src/data_converter_setup.c
View File

@@ -37,7 +37,7 @@ extern adi_cms_jesd_param_t jrx_param[];
extern adi_cms_jesd_param_t jtx_param[][2];
extern uint8_t jtx_chip_dcm[][2];
/*============= END DATA ====================*/
void set_lane_cal(int lane, int pre, int post) {
void set_lane_cal(int lane, int pre, int post, int swing) {
// Select Lane
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x24, lane);
@@ -45,6 +45,10 @@ void set_lane_cal(int lane, int pre, int post) {
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x418, pre);
// Update Postcursor 0 - 32 Valid (~0.22dB steps)
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x414, post);
// UPdate Drive Strength
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x508, swing);
// Update RX Equalizer Setting 0 = DFE 1 = LPM
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x608, 0);
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x60C, 1);
@@ -57,20 +61,79 @@ void set_lane_cal(int lane, int pre, int post) {
}
void print_rx_ila() {
xil_printf(" CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 \r\n");
for (int i = 0; i < 8; i++) {
xil_printf("Lane %2d ILA: ", i);
for (int j = 0; j < 8; j++) {
xil_printf("0x%08x ", Xil_In32(JESD_RX + 0x400 + i * 0x080 + 0x30 + j*4));
}
xil_printf("\r\n");
}
}
void reset_jesd() {
uint32_t gpo = Xil_In32(GPO_REG);
Xil_Out32(GPO_REG, gpo | ALL_JESD_RST);
vTaskDelay(100);
Xil_Out32(GPO_REG, gpo);
// Wait for reset to complete
xil_printf("Wait for RX to complete reset\r\n");
int val = 1;
while (val) {
val = Xil_In32(JESD_RX + RESET_REG);
xil_printf("rx reset state: 0x%x\r\n", val);
xil_printf("GPI: 0x%x\r\n", Xil_In32(GPI_REG));
vTaskDelay(10);
}
xil_printf("Wait for TX to complete reset\r\n");
val = 1;
while (val) {
val = Xil_In32(JESD_TX + RESET_REG);
xil_printf("tx reset state: 0x%x\r\n", val);
vTaskDelay(10);
}
}
void check_jesd_core_clk() {
uint32_t gpi = Xil_In32(GPI_REG);
uint32_t jesd_core_clk_locked = gpi & 0x8;
if (jesd_core_clk_locked == 0) {
// Not locked, try the other clock input
xil_printf("JESD Core Clk not locked!!! Trying other clock 0x%x\r\n", gpi);
uint32_t gpo = Xil_In32(GPO_REG);
gpo |= JESD_CORE_CLK_SEL;
Xil_Out32(GPO_REG, gpo);
vTaskDelay(100);
uint32_t gpi = Xil_In32(GPI_REG);
jesd_core_clk_locked = gpi & 0x8;
}
if (jesd_core_clk_locked) {
xil_printf("JESD Core Clk Locked!\r\n");
} else {
xil_printf("JESD Core Clk Locked FAILED!\r\n");
vTaskDelay(1000);
}
}
adi_ad9081_device_t * ad9081_dev_ptr;
void setup_data_converter() {
// Reset Ethernet
setBit(0x40050008, 15);
setBit(GPO_REG, 15);
vTaskDelay(1);
clearBit(0x40050008, 15);
clearBit(GPO_REG, 15);
ad9081_hal_init();
hmc7044_init();
// select use case
int uc = 1;
int uc = 0;
uint64_t app_jrx_lane_rate = 0;
uint64_t app_jtx_lane_rate[2] = {0};
@@ -139,19 +202,27 @@ void setup_data_converter() {
.invert_mask = 0x00,
.lane_mapping = { { 5, 7, 0, 1, 2, 3, 4, 6 }, { 2, 0, 7, 7, 7, 7, 3, 1 } }, /* link0, link1 */
// .lane_mapping = { { 5, 7, 0, 1, 2, 3, 4, 6 }, { 2, 0, 7, 7, 7, 7, 3, 1 } }, /* link0, link1 */ //204B // 5, 7, 0, 1, 2, 3, 4, 6
// .lane_mapping = { { 0, 1, 2, 3, 4, 5, 6, 7 }, { 2, 0, 7, 7, 7, 7, 3, 1 } }, /* link0, link1 */ //204B // 2, 3, 4, 5, 6, 0, 7, 1
// .lane_mapping = { { 2, 1, 0, 3, 4, 5, 6, 7 }, { 2, 0, 7, 7, 7, 7, 3, 1 } }, /* link0, link1 */ //204B // 2, 3, 4, 5, 6, 0, 7, 1
// .lane_mapping = { { 2, 3, 0, 1, 4, 5, 6, 7 }, { 2, 0, 7, 7, 7, 7, 3, 1 } }, /* link0, link1 */ //204B // 2, 3, 4, 5, 6, 0, 7, 1
// .lane_mapping = { { 0, 1, 4, 5, 2, 3, 6, 7 }, { 2, 0, 7, 7, 7, 7, 3, 1 } }, /* link0, link1 */ //204B
},
.des_settings = { /* ad9081 jrx */
.boost_mask = 0xff,
.boost_mask = 0xFF,
.invert_mask = 0x00,
.ctle_filter = { 2, 2, 2, 2, 2, 2, 2, 2 },
// .ctle_filter = { 4, 4, 4, 4, 4, 4, 4, 4 },
.cal_mode = AD9081_CAL_MODE_RUN,
.ctle_coeffs = {{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}}, /* CTLE 1-4 for lanes 0-7 */
.lane_mapping = { { 7, 5, 0, 1, 6, 2, 3, 4 }, { 4, 5, 6, 7, 0, 1, 2, 3 } }, /* link0, link1 */
}
},
.clk_info = {
// .sysref_mode = SYSREF_NONE,
.sysref_mode = SYSREF_CONT,
.sysref_mode = SYSREF_NONE,
// .sysref_mode = SYSREF_ONESHOT,
// .sysref_mode = SYSREF_CONT,
}
};
@@ -183,33 +254,52 @@ void setup_data_converter() {
// configure 7044 to generate clock
uint64_t ad9081_clk = clk_hz[uc][0];
uint64_t fpga_clk = clk_hz[uc][1];
uint64_t sysref_clk_204c = fpga_clk/32;
uint64_t sysref_clk_204 = fpga_clk/32;
if (((jrx_param[uc].jesd_jesdv == 0) && (jtx_param[uc][0].jesd_jesdv == 0))) {
sysref_clk_204 = fpga_clk/16;
}
uint64_t hmc7044_crystal_input = 100e6;
// uint64_t jesd_core_clk = 125e6;
// uint64_t jesd_core_clk = 237.5e6;
uint64_t jesd_core_clk = fpga_clk;
/* Configure HMC7044 SYSREF frequency output channels for SC1 Use Case */
ad9081_dev.clk_info.sysref_clk = &hmc7044_dev;
ad9081_dev.clk_info.sysref_ctrl = app_sysref_clk_src_sel;
/* Calculate SYSREF Freq for SC1 Use cases*/
ad9081_dev.clk_info.sysref_mode = SYSREF_CONT;
if (err = adi_ad9081_sync_sysref_frequency_set(&ad9081_dev, &sysref_clk_204c, ad9081_clk, clk_hz[uc][2], clk_hz[uc][3], tx_interp[uc][0], tx_interp[uc][1], rx_cddc_dcm[uc], rx_fddc_dcm[uc], jtx_param[uc][0].jesd_duallink, &jrx_param[uc], jtx_param[uc]), err != API_CMS_ERROR_OK)
if (((jrx_param[uc].jesd_subclass == 1) && (jtx_param[uc][0].jesd_subclass == 1))) {
ad9081_dev.clk_info.sysref_mode = SYSREF_CONT;
}
if (err = adi_ad9081_sync_sysref_frequency_set(&ad9081_dev, &sysref_clk_204, ad9081_clk, clk_hz[uc][2], clk_hz[uc][3], tx_interp[uc][0], tx_interp[uc][1], rx_cddc_dcm[uc], rx_fddc_dcm[uc], jtx_param[uc][0].jesd_duallink, &jrx_param[uc], jtx_param[uc]), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
printf("APP: SYSREF Clk: %lld\n", sysref_clk_204c);
printf("APP: SYSREF Clk: %lld\n", sysref_clk_204);
/*Configure HMC7044 to Provide Clocks For Txfe & FPGA*/
uint8_t hmc_priority[] = { 1, 0, 2, 3 };
uint16_t hmc_out_ch = HMC7044_OP_CH_0 | HMC7044_OP_CH_2 | HMC7044_OP_CH_3 | HMC7044_OP_CH_6 | HMC7044_OP_CH_8 | HMC7044_OP_CH_10 | HMC7044_OP_CH_12 | HMC7044_OP_CH_13;
uint64_t hmc_out_204c[14] = { fpga_clk, 0, ad9081_clk, sysref_clk_204c, 0, 0, jesd_core_clk, 0, fpga_clk, 0, jesd_core_clk, 0, fpga_clk, sysref_clk_204c };
uint64_t hmc_out_204[14];
hmc_out_204[0] = fpga_clk;
hmc_out_204[1] = 0;
hmc_out_204[2] = ad9081_clk;
hmc_out_204[3] = sysref_clk_204;
hmc_out_204[4] = 0;
hmc_out_204[5] = 0;
hmc_out_204[6] = jesd_core_clk;
hmc_out_204[7] = 0;
hmc_out_204[8] = fpga_clk;
hmc_out_204[9] = 0;
hmc_out_204[10] = jesd_core_clk;
hmc_out_204[11] = 0;
hmc_out_204[12] = fpga_clk;
hmc_out_204[13] = sysref_clk_204;
/* Disable SYSREF signal channels for Subclass 0 */
if (((jrx_param[uc].jesd_subclass == 0) && (jtx_param[uc][0].jesd_subclass == 0))) {
hmc_out_ch &= ~(HMC7044_OP_CH_3 | HMC7044_OP_CH_13);
hmc_out_204c[3] = 0;
hmc_out_204c[13] = 0;
hmc_out_204[3] = 0;
hmc_out_204[13] = 0;
xil_printf("Disabling Sysref!!!!!!!\r\n");
}
if (err = adi_hmc7044_device_init(&hmc7044_dev), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_device_reset(&hmc7044_dev, 0), err != API_CMS_ERROR_OK)
@@ -241,7 +331,7 @@ void setup_data_converter() {
if (err = adi_hmc7044_sysref_config_set(&hmc7044_dev, HMC7044_SYSREF_CONTINUOUS_MODE), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_clk_config(&hmc7044_dev, HMC7044_CLK_IN_0, hmc_priority, hmc7044_crystal_input, hmc7044_crystal_input, hmc_out_ch, hmc_out_204c), err != API_CMS_ERROR_OK) {
if (err = adi_hmc7044_clk_config(&hmc7044_dev, HMC7044_CLK_IN_0, hmc_priority, hmc7044_crystal_input, hmc7044_crystal_input, hmc_out_ch, hmc_out_204), err != API_CMS_ERROR_OK) {
if (err == API_CMS_ERROR_INVALID_PARAM)
printf("APP: HMC7044: Invalid param passed.\n");
error_print(__LINE__, err);
@@ -263,6 +353,7 @@ void setup_data_converter() {
error_print(__LINE__, err);
}
printf("APP: Reference Clocks Configured\n");
// check_jesd_core_clk();
//--------------------------------------------------------------------------------------------------------------------
/* AD9081 Device Data Path Configuration Sequenece
@@ -321,11 +412,18 @@ void setup_data_converter() {
// // DAC NCO TEST MODE!!!!!!
// xil_printf("!!!!!!!!!!! DAC NCO TEST MODE !!!!!!!!!!!!!!!!!!!!!!!\r\n");
// if (err = adi_ad9081_device_startup_nco_test_mode(&ad9081_dev, tx_interp[uc][0], tx_interp[uc][1], tx_dac_chan_xbar[uc],
// tx_main_shift[uc], tx_chan_shift[uc], &jrx_param[uc], (uint16_t)pow(10, ((0 + 20 * log10(0x5a82)) / 20))), err != API_CMS_ERROR_OK)
// return err;
// // DC Offset from examples was 0x5a82
// err = adi_ad9081_device_startup_nco_test_mode(&ad9081_dev,
// tx_interp[uc][0],
// tx_interp[uc][1],
// tx_dac_chan_xbar[uc],
// tx_main_shift[uc],
// tx_chan_shift[uc],
// &jrx_param[uc],
// (uint16_t)pow(10, ((0 + 20 * log10(0x5a82)) / 20)));
// if (err != API_CMS_ERROR_OK) {
// error_print(__LINE__, err);
// }
/* start ad9081 tx */
if (err = adi_ad9081_device_startup_tx(&ad9081_dev, tx_interp[uc][0], tx_interp[uc][1], tx_dac_chan_xbar[uc],
@@ -351,42 +449,40 @@ void setup_data_converter() {
}
/* Configure Synchronization Options as per Application Use-case*/
/* By Default Application uses Subclass 0 and Internal Sysref Synchronization*/
/* Note 21/26/27 Are examples of Subclass 1*/
printf("APP: JESD RX Synchronization Mode: %s\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
/* Configure Sysref Receiver and Input mode */
if (err = adi_ad9081_sync_sysref_input_config_set(&ad9081_dev, COUPLING_AC, SIGNAL_CML, 0, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Configure cddc nco sync */
if (err = adi_ad9081_adc_ddc_coarse_sync_enable_set(&ad9081_dev, AD9081_ADC_CDDC_ALL, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_adc_ddc_coarse_sync_next_set(&ad9081_dev, AD9081_ADC_CDDC_ALL, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_adc_ddc_coarse_trig_nco_reset_enable_set(&ad9081_dev, AD9081_ADC_CDDC_ALL, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Perform oneshot sync */
if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 1), err != API_CMS_ERROR_OK){
if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
printf("APP: JESD Oneshot Synchronization Not Completed\n");
xil_printf("APP: JESD RX Synchronization Mode: %s\r\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
if (jtx_param[uc][0].jesd_subclass == 1) {
/* Configure Sysref Receiver and Input mode */
if (err = adi_ad9081_sync_sysref_input_config_set(&ad9081_dev, COUPLING_AC, SIGNAL_CML, 0, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Configure cddc nco sync */
if (err = adi_ad9081_adc_ddc_coarse_sync_enable_set(&ad9081_dev, AD9081_ADC_CDDC_ALL, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_adc_ddc_coarse_sync_next_set(&ad9081_dev, AD9081_ADC_CDDC_ALL, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_adc_ddc_coarse_trig_nco_reset_enable_set(&ad9081_dev, AD9081_ADC_CDDC_ALL, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Perform oneshot sync */
if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 1), err != API_CMS_ERROR_OK){
if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
printf("APP: JESD Oneshot Synchronization Not Completed\n");
}
error_print(__LINE__, err);
}
if (err = adi_ad9081_jesd_sysref_monitor_phase_get(&ad9081_dev, &phase), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
printf("APP: Phase offset between incoming SYSREF and internal LMFC/LEMC: %d DAC clock units\n", phase);
} else {
/* Power down Sysref Receiver circuitry*/
if (err = adi_ad9081_jesd_sysref_input_mode_set(&ad9081_dev, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, COUPLING_AC), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Perform oneshot sync */
if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 0), err != API_CMS_ERROR_OK){
if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
xil_printf("APP: JESD Oneshot Synchronization Not Completed\r\n");
}
error_print(__LINE__, err);
}
error_print(__LINE__, err);
}
if (err = adi_ad9081_jesd_sysref_monitor_phase_get(&ad9081_dev, &phase), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
printf("APP: Phase offset between incoming SYSREF and internal LMFC/LEMC: %d DAC clock units\n", phase);
printf("APP: JESD RX Synchronization Mode: %s\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
/* Power down Sysref Receiver circuitry*/
if (err = adi_ad9081_jesd_sysref_input_mode_set(&ad9081_dev, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, COUPLING_AC), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Perform oneshot sync */
if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 0), err != API_CMS_ERROR_OK){
if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
printf("APP: JESD Oneshot Synchronization Not Completed");
}
error_print(__LINE__, err);
}
/* SYSTEM Link Bring Up Sequenece
* Check AD9081 JESD PLL Lock Status
@@ -406,32 +502,21 @@ void setup_data_converter() {
error_print(__LINE__, err);
}
// Enable RX and TX Link
if (err = adi_ad9081_jesd_tx_link_enable_set(&ad9081_dev, (jtx_param[uc][0].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
vTaskDelay(100);
uint16_t status;
if (err = adi_ad9081_jesd_tx_link_status_get(&ad9081_dev, AD9081_LINK_0, &status), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
xil_printf("Link Status 0x%x\r\n", status);
// // ILA TEST MODE
// adi_ad9081_jesd_tx_ilas_test_mode_enable_set(&ad9081_dev, AD9081_LINK_0, 1);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
//
// /* calibrate jrx when lane rate is high for 204c */
// printf("APP: Run JESD RX 204C Calibration & Enable TX Path Links\n");
// if ((jrx_param[uc].jesd_l > 0) && (jrx_param[uc].jesd_jesdv == 2) && ((clk_hz[uc][1] * 66) > AD9081_JESDRX_204C_CAL_THRESH)) {
// if (err = adi_ad9081_jesd_rx_calibrate_204c(&ad9081_dev, 1, 0x00, (ad9081_dev.serdes_info.des_settings.cal_mode == AD9081_CAL_MODE_RUN_AND_SAVE) ? 0 : 1), err != API_CMS_ERROR_OK) {
// printf("APP: ad9081 JESD RX Calibration Error\n");
// error_print(__LINE__, err);
// }
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// }
#ifdef IBERT_TESTING
adi_ad9081_jesd_tx_phy_prbs_test(&ad9081_dev, AD9081_LINK_ALL, PRBS31);
@@ -440,70 +525,71 @@ void setup_data_converter() {
#ifndef IBERT_TESTING
// Update FPGA TX Transceiver settings
set_lane_cal(0, 0, 0);
set_lane_cal(1, 10, 5);
set_lane_cal(2, 5, 0);
set_lane_cal(3, 0, 0);
set_lane_cal(4, 0, 0);
set_lane_cal(5, 0, 0);
set_lane_cal(6, 12, 0);
set_lane_cal(7, 0, 0);
set_lane_cal(0, 0, 0, 11);
set_lane_cal(1, 10, 5, 11);
set_lane_cal(2, 5, 0, 11);
set_lane_cal(3, 0, 0, 11);
set_lane_cal(4, 0, 0, 11);
set_lane_cal(5, 0, 0, 11);
set_lane_cal(6, 12, 0, 11);
set_lane_cal(7, 0, 0, 11);
// set_lane_cal(0, 9, 0, 7);
// set_lane_cal(1, 9, 0, 7);
// set_lane_cal(2, 9, 0, 7);
// set_lane_cal(3, 9, 0, 7);
// set_lane_cal(4, 9, 0, 7);
// set_lane_cal(5, 9, 0, 7);
// set_lane_cal(6, 9, 0, 7);
// set_lane_cal(7, 9, 0, 7);
vTaskDelay(100);
int subclass = jtx_param[uc][0].jesd_subclass;
int jesd_version = jtx_param[uc][0].jesd_jesdv;
xil_printf("GPI: 0x%x\r\n", Xil_In32(0x40050000 + 0x00C));
xil_printf("GPI: 0x%x\r\n", Xil_In32(GPI_REG));
xil_printf("Reset FPGA JESD Cores\r\n");
Xil_Out32(0x40050000 + 0x008, 0x31 | 0x300 | 0xC0);
vTaskDelay(100);
Xil_Out32(0x40050000 + 0x008, 0x31);
reset_jesd();
// Wait for reset to complete
xil_printf("Wait for RX to complete reset\r\n");
int val = 1;
while (val) {
val = Xil_In32(JESD_RX + RESET_REG);
xil_printf("rx reset state: 0x%x\r\n", val);
xil_printf("GPI: 0x%x\r\n", Xil_In32(0x40050000 + 0x00C));
vTaskDelay(10);
}
xil_printf("RX IP Config 0x%x\r\n", Xil_In32(JESD_RX + 4));
xil_printf("TX IP Config 0x%x\r\n", Xil_In32(JESD_TX + 4));
xil_printf("Wait for TX to complete reset\r\n");
val = 1;
while (val) {
val = Xil_In32(JESD_TX + RESET_REG);
xil_printf("tx reset state: 0x%x\r\n", val);
vTaskDelay(10);
}
// for (int i = 0; i < 8; i++){
// uint32_t val0 = Xil_In32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x418);
// uint32_t val1 = Xil_In32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x414);
// uint32_t val2 = Xil_In32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x608);
// xil_printf("Lane %d, Pre %d, Post %d, RX %d\r\n", i, val0, val1, val2);
// }
xil_printf("Changing MB in EMB\r\n");
Xil_Out32(JESD_TX + CTRL_MB_IN_EMB, 1);
Xil_Out32(JESD_RX + CTRL_MB_IN_EMB, 1);
xil_printf("Changing Subclass\r\n");
Xil_Out32(JESD_TX + 0x34, subclass);
Xil_Out32(JESD_RX + 0x34, subclass);
xil_printf("Changing Meta\r\n");
Xil_Out32(JESD_TX + 0x34, 0);
Xil_Out32(JESD_RX + 0x34, 0);
xil_printf("Changing Ctrl Sysref\r\n");
Xil_Out32(JESD_TX + 0x50, 2);
Xil_Out32(JESD_RX + 0x50, 2);
Xil_Out32(JESD_TX + 0x50, 0);
Xil_Out32(JESD_RX + 0x50, 0);
if (subclass == 1) {
Xil_Out32(JESD_TX + 0x50, 2);
Xil_Out32(JESD_RX + 0x50, 2);
}
if (jesd_version == JESD_204C) {
// 204C
xil_printf("Changing MB in EMB\r\n");
Xil_Out32(JESD_TX + CTRL_MB_IN_EMB, 1);
Xil_Out32(JESD_RX + CTRL_MB_IN_EMB, 1);
xil_printf("Changing Meta\r\n");
Xil_Out32(JESD_TX + 0x34, 0);
Xil_Out32(JESD_RX + 0x34, 0);
// Xil_Out32(JESD_TX + 0x34, 3); // FEC
// Xil_Out32(JESD_RX + 0x34, 3); // FEC
}
if (jesd_version == JESD_204B) {
//204B
xil_printf("204B CTRL_8B10B_CFG\r\n");
Xil_Out32(JESD_TX + 0x3C, 0x03031F01);
Xil_Out32(JESD_RX + 0x3C, 0x03031F01);
}
Xil_Out32(JESD_RX + CTRL_RX_BUF_ADV, 0);
val = Xil_In32(JESD_RX + CTRL_RX_BUF_ADV);
uint32_t val = Xil_In32(JESD_RX + CTRL_RX_BUF_ADV);
if (val != 0) {
xil_printf("ERROR. Buffer Advance (RX) not updated.\r\n");
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
@@ -511,57 +597,67 @@ void setup_data_converter() {
}
xil_printf("Reset both modules to update configuration\r\n");
Xil_Out32(0x40050000 + 0x008, 0x31 | 0x300 | 0xC0);
vTaskDelay(100);
Xil_Out32(0x40050000 + 0x008, 0x31);
reset_jesd();
// Wait for reset to complete
xil_printf("Wait for RX to complete reset\r\n");
val = 1;
while (val) {
val = Xil_In32(JESD_RX + RESET_REG);
xil_printf("rx reset state: 0x%x\r\n", val);
xil_printf("GPI: 0x%x\r\n", Xil_In32(0x40050000 + 0x00C));
vTaskDelay(10);
}
xil_printf("Wait for TX to complete reset\r\n");
val = 1;
while (val) {
val = Xil_In32(JESD_TX + RESET_REG);
xil_printf("tx reset state: 0x%x\r\n", val);
vTaskDelay(10);
}
xil_printf("Wait for Block Sync\r\n");
val = 0;
while ((val & STATUS_SH_LOCK_BIT) != STATUS_SH_LOCK_BIT) {
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
if (jesd_version == JESD_204C) {
xil_printf("Wait for Block Sync\r\n");
val = 0;
while ((val & STATUS_SH_LOCK_BIT) != STATUS_SH_LOCK_BIT) {
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
vTaskDelay(200);
}
xil_printf("* Block sync achieved\r\n");
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
vTaskDelay(100);
xil_printf("Wait for Extended Multiblock lock\r\n");
val = 0;
while ((val & STATUS_EMB_LOCK_BIT) != STATUS_EMB_LOCK_BIT) {
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
xil_printf("RX EMB: 0x%x\r\n", Xil_In32(JESD_RX + CTRL_MB_IN_EMB));
uint8_t data;
// adi_ad9081_hal_bf_set(&ad9081_dev, 0x00000667, BF_JTX_CRC_FEC_REVERSE_CFG_INFO, 1);
adi_ad9081_hal_reg_get(&ad9081_dev, 0x00000667, &data);
xil_printf("0x00000667: 0x%x\r\n", data);
// for (int i = 0; i < 8; i++) {
// // Clear Error Counts
// uint32_t err_cnt = Xil_In32(JESD_RX + 0x400 + i * 0x080 + 0x10);
// xil_printf(" Lane %d STAT_RX_ERROR_CNT0 = 0x%x\r\n", err_cnt);
// }
vTaskDelay(100);
}
xil_printf("* Extended Multiblock lock achieved\r\n");
}
xil_printf("* Block sync achieved\r\n");
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
if (jesd_version == JESD_204B) {
// xil_printf("Enable TX data and command stream\r\n");
// Xil_Out32(JESD_TX + CTRL_ENABLE_REG, ENABLE_DATA_CMD);
//
// xil_printf("Enable RX data and command stream\r\n");
// Xil_Out32(JESD_RX + CTRL_ENABLE_REG, ENABLE_DATA_CMD);
xil_printf("Wait for Extended Multiblock lock\r\n");
val = 0;
while ((val & STATUS_EMB_LOCK_BIT) != STATUS_EMB_LOCK_BIT) {
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
xil_printf("RX EMB: 0x%x\r\n", Xil_In32(JESD_RX + CTRL_MB_IN_EMB));
val = 0;
while ((val & 0x7000) != 0x7000) {
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX 204B STAT_RX_ERR: 0x%x\r\n", Xil_In32(JESD_RX + 0x58));
xil_printf("RX 204B STAT_RX_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x5C));
uint16_t status;
if (err = adi_ad9081_jesd_tx_link_status_get(&ad9081_dev, AD9081_LINK_0, &status), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
xil_printf("Link Status 0x%x\r\n", status);
xil_printf("GPI: 0x%x\r\n", Xil_In32(GPI_REG));
print_rx_ila();
// for (int i = 0; i < 8; i++) {
// // Clear Error Counts
// uint32_t err_cnt = Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x10);
// xil_printf(" Lane %d STAT_RX_ERROR_CNT0 = 0x%x\r\n", err_cnt);
// }
vTaskDelay(100);
vTaskDelay(400);
}
}
xil_printf("* Extended Multiblock lock achieved\r\n");
xil_printf("Enable TX data and command stream\r\n");
Xil_Out32(JESD_TX + CTRL_ENABLE_REG, ENABLE_DATA_CMD);
@@ -572,7 +668,7 @@ void setup_data_converter() {
vTaskDelay(100);
xil_printf("GPI: 0x%x\r\n", Xil_In32(0x40050000 + 0x00C));
xil_printf("GPI: 0x%x\r\n", Xil_In32(GPI_REG));
xil_printf("RX Version: 0x%x\r\n", Xil_In32(JESD_RX + 0x000));
xil_printf("RX Config: 0x%x\r\n", Xil_In32(JESD_RX + 0x004));
@@ -601,42 +697,56 @@ void setup_data_converter() {
#endif
// Toggle JESD RX Enable
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* calibrate jrx when lane rate is high for 204c */
printf("APP: Run JESD RX 204C Calibration & Enable TX Path Links\n");
if ((jrx_param[uc].jesd_l > 0) && (jrx_param[uc].jesd_jesdv == 2) && ((clk_hz[uc][1] * 66) > AD9081_JESDRX_204C_CAL_THRESH)) {
if (err = adi_ad9081_jesd_rx_calibrate_204c(&ad9081_dev, 1, 0x00, (ad9081_dev.serdes_info.des_settings.cal_mode == AD9081_CAL_MODE_RUN_AND_SAVE) ? 0 : 1), err != API_CMS_ERROR_OK) {
printf("APP: ad9081 JESD RX Calibration Error\n");
// if (1) {
xil_printf("APP: Run JESD RX 204C Calibration & Enable TX Path Links\r\n");
// if (err = adi_ad9081_jesd_rx_calibrate_204c(&ad9081_dev, 1, 0x00, (ad9081_dev.serdes_info.des_settings.cal_mode == AD9081_CAL_MODE_RUN_AND_SAVE) ? 0 : 1), err != API_CMS_ERROR_OK) {
// xil_printf("APP: ad9081 JESD RX Calibration Error\r\n");
// error_print(__LINE__, err);
// }
//
if (err = adi_ad9081_jesd_rx_calibrate_204c(&ad9081_dev, 1, 0x00, 1), err != API_CMS_ERROR_OK) {
xil_printf("APP: ad9081 JESD RX Calibration Error\r\n");
error_print(__LINE__, err);
}
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_calibrate_204c(&ad9081_dev, 1, 0xFF, 1), err != API_CMS_ERROR_OK) {
// xil_printf("APP: ad9081 JESD RX Calibration Error\r\n");
// error_print(__LINE__, err);
// }
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
}
#ifndef IBERT_TESTING
for (int i = 0; i < 8; i++) {
// Clear Error Counts
Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x10);
Xil_In32(JESD_RX + 0x400 + i * 0x080 + 0x10);
}
vTaskDelay(100);
for (int i = 0; i < 8; i++) {
xil_printf("Lane %d Buf Level: 0x%x\r\n", i, Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x0));
xil_printf("Lane %d Stat 0: 0x%x\r\n", i, Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x10));
xil_printf("Lane %d Stat 1: 0x%x\r\n", i, Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x14));
xil_printf("Lane %d Buf Level: 0x%x\r\n", i, Xil_In32(JESD_RX + 0x400 + i * 0x080 + 0x0));
xil_printf("Lane %d Stat 0: 0x%x\r\n", i, Xil_In32(JESD_RX + 0x400 + i * 0x080 + 0x10));
xil_printf("Lane %d Stat 1: 0x%x\r\n", i, Xil_In32(JESD_RX + 0x400 + i * 0x080 + 0x14));
}
#endif
#ifdef IBERT_TESTING
int cal_count = 0;
while (1) {
adi_ad9081_jesd_rx_phy_prbs_test(&ad9081_dev, PRBS31, 100);
xil_printf("Check PRBS Errors\r\n");
@@ -645,6 +755,17 @@ void setup_data_converter() {
adi_ad9081_jesd_rx_phy_prbs_test_result_get(&ad9081_dev, i, &prbs_res);
xil_printf(" Lane %d, Errors %d\r\n", i, prbs_res.phy_prbs_err_cnt);
}
cal_count++;
// if (cal_count > 9) {
// cal_count = 0;
// if (err = adi_ad9081_jesd_rx_calibrate_204c(&ad9081_dev, 1, 0x00, 1), err != API_CMS_ERROR_OK) {
// xil_printf("APP: ad9081 JESD RX Calibration Error\r\n");
// error_print(__LINE__, err);
// }
// }
}
#endif

4
vitis/radar/src/main.c
View File

@@ -114,7 +114,7 @@ void main_task( void *pvParameters ) {
setup_data_converter();
while (1) {
toggleBit(0x40050008, 0); // Toggle LED
toggleBit(GPO_REG, 0); // Toggle LED
vTaskDelay(100);
}
@@ -123,7 +123,7 @@ void main_task( void *pvParameters ) {
int main(void) {
xil_printf("\n\r\n\r================= Start ====================\n\r\n\r");
Xil_Out32(0x40050008, 0x11);
Xil_Out32(GPO_REG, 0x11);
xTaskCreate( status_task,
( const char * ) "status",

3
vitis/radar/src/project.h
View File

@@ -78,6 +78,9 @@ extern adi_ad9081_device_t * ad9081_dev_ptr;
#define STAT_RX_BUF_LVL6 0x700
#define STAT_RX_BUF_LVL7 0x780
#define JESD_204B 1
#define JESD_204C 2
int32_t rf_spi_write(int dev_sel, int num_bits, int data);
#endif

40
vitis/radar/src/radar_manager_icd.c
View File

@@ -122,7 +122,7 @@ void radar_manager_parse_message(u8 * msgBuffer)
case SET_AD9081_DAC_NCO:
{
ncoConfigType *msg = (ncoConfigType *)msgBuffer;
xil_printf("Set DAC NCO, Ch %d, Freq %d\r\n", msg->channel, (int)msg->frequency);
xil_printf("Set DAC NCO, Ch %d, Freq %d\r\n", msg->channel, (int)(msg->frequency / 1e3));
adi_ad9081_dac_duc_nco_set(ad9081_dev_ptr, AD9081_DAC_0 << msg->channel, AD9081_DAC_CH_NONE, msg->frequency);
}
break;
@@ -130,7 +130,7 @@ void radar_manager_parse_message(u8 * msgBuffer)
case SET_AD9081_ADC_NCO:
{
ncoConfigType *msg = (ncoConfigType *)msgBuffer;
xil_printf("Set ADC NCO, Ch %d, Freq %d\r\n", msg->channel, (int)msg->frequency);
xil_printf("Set ADC NCO, Ch %d, Freq %d\r\n", msg->channel, (int)(msg->frequency / 1e3));
adi_ad9081_adc_ddc_coarse_nco_set(ad9081_dev_ptr, AD9081_ADC_CDDC_0 << msg->channel, msg->frequency);
}
break;
@@ -142,6 +142,42 @@ void radar_manager_parse_message(u8 * msgBuffer)
}
break;
case SET_LANE_MAPPING:
{
laneMappingType *msg = (laneMappingType *)msgBuffer;
adi_ad9081_jesd_tx_link_enable_set(ad9081_dev_ptr, AD9081_LINK_0, 0);
adi_ad9081_jesd_tx_lanes_xbar_set(ad9081_dev_ptr, AD9081_LINK_0, msg->lane_map);
adi_ad9081_jesd_tx_link_enable_set(ad9081_dev_ptr, AD9081_LINK_0, 1);
reset_jesd();
}
break;
case AD9081_REG_WRITE:
{
writeRegType *msg = (writeRegType *)msgBuffer;
adi_ad9081_hal_reg_set(ad9081_dev_ptr, msg->addr, msg->data);
}
break;
case AD9081_REG_READ:
{
readRegType *msg = (readRegType *)msgBuffer;
readRespType resp;
uint8_t val;
adi_ad9081_hal_reg_get(ad9081_dev_ptr, msg->addr, &val);
resp.header.fsync = FSYNC;
resp.header.type = AXI_READ_RESP;
resp.header.length = sizeof(resp);
resp.data = val;
send_data((u8 *)&resp, sizeof(resp));
}
break;
default:
DEBUG_PRINT("Unknown Type 0x%04X!\r\n", header->type);
break;

10
vitis/radar/src/radar_manager_icd.h
View File

@@ -18,6 +18,9 @@ void radar_manager_parse_message(u8 * msgBuffer);
#define RF_SPI_WRITE 7
#define SET_AD9081_DAC_NCO 128
#define SET_AD9081_ADC_NCO 129
#define SET_LANE_MAPPING 130
#define AD9081_REG_WRITE 131
#define AD9081_REG_READ 132
#define HDR_FLAG_REQ_ACK 0x01
@@ -63,7 +66,7 @@ typedef struct {
typedef struct {
headerType header;
unsigned int channel;
float frequency;
int64_t frequency;
} ncoConfigType;
typedef struct {
@@ -73,6 +76,11 @@ typedef struct {
unsigned int data;
} rfSpiWriteType;
typedef struct {
headerType header;
uint8_t lane_map[8];
} laneMappingType;
//typedef struct {
// uint32_t num_pulses;
// uint32_t num_pulses;

28
vitis/radar/src/registers.h
View File

@@ -2,11 +2,29 @@
#define __REGISTERS_H__
#define UTIL_ADDR 0x40050000
#define UTIL_ADDR 0x40050000
#define GPO_REG (UTIL_ADDR + 0x08)
#define ETH_10G_RST 0x8000
#define JESD_CORE_CLK_SEL 0x0800
#define QSPI_FLASH_RST 0x0400
#define JESD_TX_SYS_RST 0x0200
#define JESD_RX_SYS_RST 0x0100
#define JESD_TX_CORE_RST 0x0080
#define JESD_RX_CORE_RST 0x0040
#define RESETB 0x0020
#define FMC_PWR_EN 0x0010
#define ALL_JESD_RST (JESD_TX_SYS_RST | JESD_RX_SYS_RST | JESD_TX_CORE_RST | JESD_RX_CORE_RST)
#define GPI_REG (UTIL_ADDR + 0x0C)
#define TIMING_ENGINE_ADDR 0x40051000
#define DIG_RX_ADDR 0x20000000
#define DIG_RX_STRIDE 0x10000
#define WAVEFORM_GEN_ADDR 0x40053000
#define TIMING_ENGINE_ADDR 0x40051000
#define DIG_RX_ADDR 0x20000000
#define DIG_RX_STRIDE 0x10000
#define WAVEFORM_GEN_ADDR 0x40053000
#endif

44
vitis/radar/src/uc_settings.c
View File

@@ -43,7 +43,12 @@ build a usecase parameters for a custom application.
uint64_t clk_hz[][4] = {
/*dev_ref, fpga_ref, dac_clk, adc_clk */
{ 93.75e6, 187.5e6, 9000e6, 3000e6 },
{ 118.75e6, 237.5e6, 11400e6, 3800e6 },
{ 112.5e6, 225e6, 10800e6, 3600e6 },
{ 125e6, 250e6, 6000e6, 3000e6 },
// { 125e6, 250e6, 12000e6, 4000e6 },
{ 93.75e6, 187.5e6, 9000e6, 3000e6 },
// { 100e6, 250e6, 12000e6, 4000e6 },
}; // 204B
#if !defined(AD9207_ID) && !defined(AD9209_ID)
@@ -95,32 +100,42 @@ uint64_t clk_hz[][4] = {
*
*/
#define tx_if_freq 500e6
#define rx_if_freq 500e6
#define tx_if_freq 1010e6
#define rx_if_freq 1000e6
//#define if_freq 10e6
uint8_t tx_dac_chan_xbar[][4] = { /* dac0, dac1, dac2, dac3 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 },
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 },
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 },
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 },
};
int64_t tx_main_shift[][4] = { /* dac0, dac1, dac2, dac3 */
{ tx_if_freq, tx_if_freq, tx_if_freq, tx_if_freq }, /* uc13*/
{ tx_if_freq, tx_if_freq, tx_if_freq, tx_if_freq }, /* uc13*/
{ tx_if_freq, tx_if_freq, tx_if_freq, tx_if_freq }, /* uc13*/
{ tx_if_freq, tx_if_freq, tx_if_freq, tx_if_freq }, /* uc13*/
};
int64_t tx_chan_shift[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
int8_t tx_chan_gain[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
uint8_t tx_interp[][2] = {
/* {main DUC Interpolation, Channelizer DUC Interpolation} */
{ 12, 1 }, /* uc13*/
{ 12, 1 }, /* uc13*/
{ 8, 3 }, /* uc13*/
{ 12, 2 }, /* uc13*/
};
#endif
@@ -134,6 +149,8 @@ uint8_t tx_interp[][2] = {
uint8_t rx_cddc_select[] = {
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
};
/* RX Main Path DDC NCO Frequency Configuration
@@ -148,6 +165,8 @@ int64_t rx_cddc_shift[][4] = {
/* {cddc0, cddc1, cddc2, cddc3 }*/
{ rx_if_freq, rx_if_freq, rx_if_freq, rx_if_freq}, /* uc13*/
{ rx_if_freq, rx_if_freq, rx_if_freq, rx_if_freq}, /* uc13*/
{ rx_if_freq, rx_if_freq, rx_if_freq, rx_if_freq}, /* uc13*/
{ rx_if_freq, rx_if_freq, rx_if_freq, rx_if_freq}, /* uc13*/
};
/* RX Main Path DDC Data Decimation
* List the ADC_Coarse DDCs desired data decimation
@@ -162,6 +181,8 @@ uint8_t rx_cddc_dcm[][4] = {
/*{cddc0, cddc1, cddc2, cddc3} */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
{ AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6 }, /* uc13*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
};
/* RX Main Path DDC Has Optional Complex to Real Convertor
* rx_cddc_c2r sets the enable for Complex to Real Converter per Main/Coarse DDC
@@ -176,6 +197,8 @@ uint8_t rx_cddc_dcm[][4] = {
uint8_t rx_cddc_c2r[][4] = { /* cddc0, cddc1, cddc2, cddc3 */
{ 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0 }, /* uc13*/
};
/* RX Channelizer/Fine DDC Datapath Selection
* List the ADC Fine DDCs data path for routing Data from Main/ Coarse DDC Datapth to the JESD Tx
@@ -193,6 +216,8 @@ uint8_t rx_cddc_c2r[][4] = { /* cddc0, cddc1, cddc2, cddc3 */
uint8_t rx_fddc_select[] = {
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
};
/* RX Channelizer Path DDC NCO Frequency Configuration
* List the ADC_Fine DDCs desired Frequency Shift
@@ -206,6 +231,8 @@ int64_t rx_fddc_shift[][8] = {
/* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
/* RX Channelizer Data Decimation
* List the ADC Fine DDCs desired data decimation
@@ -220,6 +247,8 @@ int64_t rx_fddc_shift[][8] = {
uint8_t rx_fddc_dcm[][8] = { /* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
{ AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, 0, 0, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, 0, 0 }, /* uc13*/
};
uint8_t rx_fddc_c2r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* uc */
@@ -243,6 +272,8 @@ uint8_t rx_fddc_c2r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* uc */
adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2] = {
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
};
/* Total Decimation Settings */
@@ -260,16 +291,23 @@ adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2] = {
uint8_t jtx_chip_dcm[][2] = {
{ 4 }, /* uc13.link0 */
{ 4 }, /* uc13.link0 */
{ 6 }, /* uc13.link0 */
{ 8 }, /* uc13.link0 */
};
adi_cms_jesd_param_t jrx_param[] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 15 }, /* uc13: txmode = 378 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 15 }, /* uc13: txmode = 378 */
{ 8, 2, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 1, 15 }, // 204B
{ 8, 2, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 1, 15 }, // 204B
};
adi_cms_jesd_param_t jtx_param[][2] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode C2R ModeS */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16, 0, 0 } }, /* uc13: rxmode = 227, link0 */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16, 0, 0 } }, /* uc13: rxmode = 227, link0 */
{ { 8, 2, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 1, 16, 0, 0 } }, // 204B
{ { 8, 2, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 1, 16, 0, 0 } }, // 204B
// { { 8, 4, 8, 2, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 16, 0, 1 } }, // 204B
};