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2 Commits
d1ccfb8357
...
086c5dd9f3
| Author | SHA1 | Date | |
|---|---|---|---|
| 086c5dd9f3 | |||
| 498c02cf18 |
36
python/waveform_generator/hdl_sim_check_results.py
Normal file
36
python/waveform_generator/hdl_sim_check_results.py
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@@ -0,0 +1,36 @@
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from matplotlib import pyplot as plt
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from ctypes import *
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import numpy as np
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def read_sim_output(filename, is_float=False):
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fid = open(filename, "r")
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lines = fid.readlines()
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fid.close()
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data = [int(line) for line in lines]
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data = np.array(data)
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if is_float:
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as_floats = c_float * data.size
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data = as_floats.from_buffer(data.astype(np.int32))
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data = np.array(data)
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return data
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def main():
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data = read_sim_output("sim_out.bin")
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data[data >= 2**15] -= 2**16
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data = data[0::2] + 1j * data[1::2]
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plt.figure()
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plt.plot(data.real)
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plt.plot(data.imag)
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plt.title('Sim Output')
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plt.grid()
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plt.show()
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if __name__ == '__main__':
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main()
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14
python/waveform_generator/hdl_sim_config.py
Normal file
14
python/waveform_generator/hdl_sim_config.py
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@@ -0,0 +1,14 @@
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def main():
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fs = 750e6
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f = 10e6
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n = 4096
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freq = f/fs * 2**31
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print(freq)
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if __name__ == '__main__':
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main()
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43
python/waveform_generator/prbs_test.py
Normal file
43
python/waveform_generator/prbs_test.py
Normal file
@@ -0,0 +1,43 @@
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from matplotlib import pyplot as plt
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def main():
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bit = list()
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start = 2
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lfsr = start
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i = 1
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values = []
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taps = [5, 4]
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# taps = [5, 4, 2, 1]
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while True:
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# fb = ((lfsr >> 5) ^ (lfsr >> 4) & 1)
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fb = 0
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for tap in taps:
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fb ^= ((lfsr >> tap) & 1)
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lfsr = ((lfsr << 1) + fb) & (2 ** 6 - 1)
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bit.append(fb)
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values.append(lfsr)
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print(i, lfsr, fb, bin(lfsr))
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if lfsr == start:
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print('repeat pattern length', i)
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break
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i = i + 1
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print('Duplicate Check', len(values), len(set(values)))
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# bit = [float(i) for i in bit]
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# for i in range(2 ** 6 - 1):
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# bit[i] = 2 * (bit[i] - 0.5)
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plt.plot(values)
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plt.title('sequence')
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plt.show()
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print("done!")
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if __name__ == '__main__':
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main()
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@@ -1,4 +1,5 @@
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import numpy as np
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from matplotlib import pyplot as plt
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# get one chip of a multi-chip OFDM waveform
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@@ -105,22 +106,67 @@ def get_pulse_params(n_tx, n_rx, f_samp, n_samp_chip, n_f, n_f_pulse, n_sub_cpi,
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f_sa_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = f_sa[
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n_tx_ind, n_sub_cpi_ind, n_f_pulse_ind
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]
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return
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return baseband, start_phase, f_sa, chip_samples, chip_center_dmux, chip_lower_dmux, chip_upper_dmux, time_shift_dmux, f_sa_dmux
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def wg_ofdm():
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# wp = inputs.wp.proto # just to make code easier to read
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n_f = 4
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n_f_pulse = 4
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n_f = 8
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n_f_pulse = 8
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do_random = False
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do_agile = False
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n_sub_cpi = 1
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n_tx = 1
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n_rx = 2
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n_pol = 2
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n_samp = 32
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n_samp = 64
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n_samp_chip = 8
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f_samp = 46875000.0
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tx_sample_rate_multiplier = 16
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f_samp = 46875000.0
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f_samp = 750e6 / tx_sample_rate_multiplier
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# Confused about f_samp, n_samp_chip, and tx_sample_rate_multiplier
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# I would have expected something like n_chips and n_samples_per_chip
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# What is the total bandwidth of the approximated LFM, how is that decided
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# Like more, finer spaced chips
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# Charlie says params are normalized to RX sample rate
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# f_samp is decimated RX sample rate
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# n_samp is length of pulse in decimated rx_samples
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# n_samp_chip
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# n_samp = 512
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# n_samp_chip = 128
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# tx_sample_rate_multiplier = 1
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# f_samp = 46875000.0
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# Start with 32 bit accumulator
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# phase is intended to be continuation of previous chip
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# so maybe start phase for just first pulse
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# put in for each chip but make bypassable
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# Think of time bandwidth product
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# num chips is sqrt of time bandwidth product to start
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# each chip must be power of 2
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# PRBS length has to match number of chips (need to use every chip in every subcpi)
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# total number of chips
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# number of chips per pulse
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# num_pulses_in_sub_cpi = total number of chips / number of chips per pulse / number of transmitters
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# number of transmitters
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# del_f between chips
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# Start freq
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# Seed
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n_gen_pulses = 1
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rng = np.random.default_rng(seed=42)
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perm_list = []
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@@ -184,49 +230,34 @@ def wg_ofdm():
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for n_p in range(unique_sub_cpi):
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perm_list_full.append(perm_list[n_p % unique_sub_cpi])
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# pp_list = PulseParamsList(
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# pulse_params=[get_pulse_params(wp=wp, perm=p) for p in perm_list_full]
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# )
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[get_pulse_params(n_tx, n_rx, f_samp, n_samp_chip, n_f, n_f_pulse, n_sub_cpi, n_pol, p) for p in perm_list_full]
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subpulses = np.ndarray(
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shape=(
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unique_sub_cpi,
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n_tx * n_pol,
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n_sub_cpi,
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n_samp * tx_sample_rate_multiplier,
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2, # I/Q
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),
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dtype=np.uint16,
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)
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amplitude_quant = 2 ** (16 - 1) - 1
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zero_quant = 0
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# This generates transmit waveforms for the whole CPI
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for n_cpi in range(unique_sub_cpi):
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pulse, _phase = get_waveform(
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np.array(
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pp_list.pulse_params[n_cpi].baseband.elements, dtype=np.double
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).reshape(tuple(pp_list.pulse_params[n_cpi].baseband.dimensions)),
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np.array(
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pp_list.pulse_params[n_cpi].start_phase.elements, dtype=np.double
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).reshape(tuple(pp_list.pulse_params[n_cpi].start_phase.dimensions)),
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n_tx * n_pol,
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n_sub_cpi,
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n_f_pulse,
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n_samp_chip * tx_sample_rate_multiplier,
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n_samp * tx_sample_rate_multiplier,
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f_samp * tx_sample_rate_multiplier,
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)
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p = perm_list_full[0]
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baseband, start_phase, f_sa, chip_samples, chip_center_dmux, chip_lower_dmux, chip_upper_dmux, time_shift_dmux, f_sa_dmux = (
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get_pulse_params(n_tx, n_rx, f_samp, n_samp_chip, n_f, n_f_pulse, n_sub_cpi, n_pol, p))
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subpulses[n_cpi, ..., 0] = np.round(
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(amplitude_quant * np.real(pulse) + zero_quant).astype(np.uint16)
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)
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subpulses[n_cpi, ..., 1] = np.round(
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(amplitude_quant * np.imag(pulse) + zero_quant).astype(np.uint16)
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)
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print(baseband/1e6)
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pulse, _phase = get_waveform(baseband,
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start_phase,
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n_tx * n_pol,
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n_sub_cpi,
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n_f_pulse,
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n_samp_chip * tx_sample_rate_multiplier,
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n_samp * tx_sample_rate_multiplier,
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f_samp * tx_sample_rate_multiplier)
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pulse = np.squeeze(pulse)
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plt.figure()
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plt.plot(pulse[0, :].real)
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plt.plot(pulse[0, :].imag)
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plt.figure()
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plt.plot(pulse[1, :].real)
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plt.plot(pulse[1, :].imag)
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plt.show()
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return
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159
radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv
Normal file
159
radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv
Normal file
@@ -0,0 +1,159 @@
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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module gen_ofdm # (
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parameter integer AXI_ADDR_WIDTH = 32,
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parameter integer AXI_DATA_WIDTH = 32
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)
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(
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input wire clk,
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input wire reset,
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axi4l_intf.slave ctrl_if,
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input wire start_pulse,
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output wire [127:0] iq_out,
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output wire iq_out_valid
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);
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// ------------------------------
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// AXIL Decode
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// ------------------------------
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wire [AXI_ADDR_WIDTH-1 : 0] raddr;
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wire [AXI_ADDR_WIDTH-1 : 0] waddr;
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wire rden;
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wire wren;
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wire [AXI_DATA_WIDTH-1 : 0] wdata;
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reg [AXI_DATA_WIDTH-1 : 0] rdata;
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axil_slave
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# (
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.DATA_WIDTH(AXI_DATA_WIDTH),
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.ADDR_WIDTH(AXI_ADDR_WIDTH)
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) axil_slave_i
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(
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// AXIL Slave
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.S_AXI_ACLK(ctrl_if.clk),
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.S_AXI_ARESETN(ctrl_if.resetn),
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.S_AXI_AWADDR(ctrl_if.awaddr),
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.S_AXI_AWPROT(ctrl_if.awprot),
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.S_AXI_AWVALID(ctrl_if.awvalid),
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.S_AXI_AWREADY(ctrl_if.awready),
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.S_AXI_WDATA(ctrl_if.wdata),
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.S_AXI_WSTRB(ctrl_if.wstrb),
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.S_AXI_WVALID(ctrl_if.wvalid),
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.S_AXI_WREADY(ctrl_if.wready),
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.S_AXI_BRESP(ctrl_if.bresp),
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.S_AXI_BVALID(ctrl_if.bvalid),
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.S_AXI_BREADY(ctrl_if.bready),
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.S_AXI_ARADDR(ctrl_if.araddr),
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.S_AXI_ARPROT(ctrl_if.arprot),
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.S_AXI_ARVALID(ctrl_if.arvalid),
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.S_AXI_ARREADY(ctrl_if.arready),
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.S_AXI_RDATA(ctrl_if.rdata),
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.S_AXI_RRESP(ctrl_if.rresp),
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.S_AXI_RVALID(ctrl_if.rvalid),
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.S_AXI_RREADY(ctrl_if.rready),
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.raddr(raddr),
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.waddr(waddr),
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.wren(wren),
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.rden(rden),
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.wdata(wdata),
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.rdata(rdata)
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);
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// ------------------------------
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// Config Registers
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// ------------------------------
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reg [31:0] reg_ctrl;
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reg [31:0] reg_freq;
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reg [31:0] reg_phase;
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reg [31:0] reg_chips;
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always @ (posedge ctrl_if.clk) begin
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if (~ctrl_if.resetn) begin
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reg_ctrl <= 0;
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reg_freq <= 0;
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reg_phase <= 0;
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end else begin
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if (wren) begin
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if (waddr[11:0] == 'h000) begin
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reg_ctrl <= wdata;
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end
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if (waddr[11:0] == 'h004) begin
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reg_freq <= wdata;
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end
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if (waddr[11:0] == 'h008) begin
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reg_phase <= wdata;
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end
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if (waddr[11:0] == 'h00C) begin
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reg_chips <= wdata;
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end
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// if (waddr[11:0] == 'h010) begin
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// reg_phase <= wdata;
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// end
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end
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end
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end
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wire [15:0] n_samp_chip = reg_chips[15:0];
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wire [15:0] n_chip = reg_chips[31:16];
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// ------------------------------
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// Bla
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// ------------------------------
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reg [24:0] pulse_cnt;
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reg [15:0] chip_cnt;
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reg [15:0] chip_ind;
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reg pulse_active;
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reg start_of_pulse;
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always @ (posedge clk) begin
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if (reset) begin
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chip_cnt <= 0;
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chip_ind <= 0;
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pulse_active <= 1'b0;
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start_of_pulse <= 1'b0;
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end else begin
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start_of_pulse <= 1'b0;
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if (start_pulse) begin
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chip_cnt <= 0;
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chip_ind <= 0;
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pulse_active <= 1'b1;
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start_of_pulse <= 1'b1;
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end
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if (pulse_active) begin
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chip_cnt <= chip_cnt + 1;
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if (chip_cnt == n_samp_chip - 1) begin
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chip_cnt <= 0;
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chip_ind <= chip_ind + 1;
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if (chip_ind == n_chip - 1) begin
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chip_ind <= 0;
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pulse_active = 1'b0;
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end
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end
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end
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end
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end
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gen_sine gen_sine_i (
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.clk(clk),
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.reset(reset),
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.set_phase(start_of_pulse),
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.valid(pulse_active),
|
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.phase(reg_phase),
|
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.frequency(reg_freq),
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.iq_out(iq_out),
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.iq_out_valid(iq_out_valid)
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);
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endmodule
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`resetall
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72
radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv
Normal file
72
radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv
Normal file
@@ -0,0 +1,72 @@
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`resetall
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`timescale 1ns / 1ps
|
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`default_nettype none
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// Generates 4 output samples in parallel
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// Samples are 16 bit I and 16 bit Q, 32 bits per sample
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module gen_sine
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(
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input wire clk,
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input wire reset,
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input wire set_phase,
|
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input wire valid,
|
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input wire [31:0] phase,
|
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input wire [31:0] frequency,
|
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output wire [127:0] iq_out,
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output wire iq_out_valid
|
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);
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reg set_phase_q;
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reg valid_q;
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reg valid_q2;
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reg [31:0] phase_q;
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reg [31:0] frequency_q;
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reg [127:0] iq_out_i;
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always @ (posedge clk) begin
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set_phase_q <= set_phase;
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phase_q <= phase;
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frequency_q <= frequency;
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valid_q <= valid;
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valid_q2 <= valid_q;
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end
|
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|
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genvar i;
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generate
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for (i = 0; i < 4; i = i + 1) begin
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|
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reg [31:0] phase_accum;
|
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|
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always @ (posedge clk) begin
|
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if (reset) begin
|
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phase_accum <= 0;
|
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end else if (valid_q) begin
|
||||
if (set_phase_q) begin
|
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phase_accum <= phase_q + i*frequency_q;
|
||||
end else begin
|
||||
phase_accum <= phase_accum + 4*frequency_q;
|
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end
|
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end
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end
|
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|
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|
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wire [39:0] cordic_phase_in = {{8{phase_accum[31]}}, phase_accum};
|
||||
|
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wfg_cordic wfg_cordic_i (
|
||||
.aclk(clk),
|
||||
.s_axis_phase_tvalid(valid_q2),
|
||||
.s_axis_phase_tdata(cordic_phase_in),
|
||||
.m_axis_dout_tvalid(iq_out_valid),
|
||||
.m_axis_dout_tdata(iq_out_i[i*32+31:i*32])
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
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|
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assign iq_out = iq_out_i;
|
||||
|
||||
endmodule
|
||||
`resetall
|
||||
|
||||
215
radar_alinx_kintex.srcs/sources_1/ip/axi_vip_0/axi_vip_0.xci
Normal file
215
radar_alinx_kintex.srcs/sources_1/ip/axi_vip_0/axi_vip_0.xci
Normal file
@@ -0,0 +1,215 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axi_vip_0",
|
||||
"component_reference": "xilinx.com:ip:axi_vip:1.1",
|
||||
"ip_revision": "13",
|
||||
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/axi_vip_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "axi_vip_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SUPPORTS_NARROW": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_SIZE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_BURST": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_LOCK": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_CACHE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_REGION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_QOS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_PROT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"VIP_PKG_NAME": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_INTERFACE_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_NARROW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_LOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_CACHE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_REGION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_QOS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "kintexu" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcku040" } ],
|
||||
"PACKAGE": [ { "value": "ffva1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "13" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/axi_vip_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_bready": [ { "direction": "out" } ],
|
||||
"m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_arvalid": [ { "direction": "out" } ],
|
||||
"m_axi_arready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_rvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_rready": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Master_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "m_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"RESET": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLOCK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"Master_AXI": {
|
||||
"range": "4294967296",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
190
radar_alinx_kintex.srcs/sources_1/ip/wfg_cordic/wfg_cordic.xci
Normal file
190
radar_alinx_kintex.srcs/sources_1/ip/wfg_cordic/wfg_cordic.xci
Normal file
@@ -0,0 +1,190 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "wfg_cordic",
|
||||
"component_reference": "xilinx.com:ip:cordic:6.0",
|
||||
"ip_revision": "18",
|
||||
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/wfg_cordic",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "wfg_cordic", "resolve_type": "user", "usage": "all" } ],
|
||||
"Functional_Selection": [ { "value": "Sin_and_Cos", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Architectural_Configuration": [ { "value": "Parallel", "resolve_type": "user", "usage": "all" } ],
|
||||
"Pipelining_Mode": [ { "value": "Maximum", "resolve_type": "user", "usage": "all" } ],
|
||||
"Data_Format": [ { "value": "SignedFraction", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Format": [ { "value": "Scaled_Radians", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Input_Width": [ { "value": "34", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Output_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Round_Mode": [ { "value": "Round_Pos_Inf", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Iterations": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Precision": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Coarse_Rotation": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Compensation_Scaling": [ { "value": "No_Scale_Compensation", "resolve_type": "user", "usage": "all" } ],
|
||||
"cartesian_has_tuser": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"cartesian_tuser_width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"cartesian_has_tlast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"phase_has_tuser": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"phase_tuser_width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"phase_has_tlast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"flow_control": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
|
||||
"optimize_goal": [ { "value": "Performance", "resolve_type": "user", "usage": "all" } ],
|
||||
"out_tready": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"out_tlast_behv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
|
||||
"ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_ARCHITECTURE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CORDIC_FUNCTION": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COARSE_ROTATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_FORMAT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ACLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_CARTESIAN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_PHASE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INPUT_WIDTH": [ { "value": "34", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ITERATIONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUTPUT_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PHASE_FORMAT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINE_MODE": [ { "value": "-2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRECISION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SCALE_COMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_PHASE_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_PHASE_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_PHASE_TDATA_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_CARTESIAN_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_S_AXIS_CARTESIAN_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_CARTESIAN_TDATA_WIDTH": [ { "value": "80", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_CARTESIAN_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "kintexu" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcku040" } ],
|
||||
"PACKAGE": [ { "value": "ffva1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "18" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/wfg_cordic" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axis_phase_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_phase_tdata": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"m_axis_dout_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_DOUT:S_AXIS_PHASE:S_AXIS_CARTESIAN", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_PHASE": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "5", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_phase_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_phase_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DOUT": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
119
radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv
Normal file
119
radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv
Normal file
@@ -0,0 +1,119 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
import axi_vip_pkg::*;
|
||||
import axi_vip_0_pkg::*;
|
||||
|
||||
module testbench();
|
||||
|
||||
|
||||
reg clk;
|
||||
reg reset;
|
||||
reg resetn;
|
||||
|
||||
assign resetn = ~reset;
|
||||
|
||||
localparam T = 4;
|
||||
always #(T/2) clk=~clk;
|
||||
|
||||
axi4l_intf # (
|
||||
.AXI_ADDR_WIDTH(32),
|
||||
.AXI_DATA_WIDTH(32)
|
||||
)
|
||||
ctrl_if (
|
||||
.clk(clk),
|
||||
.resetn(resetn)
|
||||
);
|
||||
|
||||
axi_vip_0_mst_t vip_mst;
|
||||
xil_axi_resp_t resp;
|
||||
|
||||
axi_vip_0 axi_vip_inst (
|
||||
.aclk(clk),
|
||||
.aresetn(resetn),
|
||||
.m_axi_awaddr( ctrl_if.awaddr ),
|
||||
.m_axi_awprot( ctrl_if.awprot ),
|
||||
.m_axi_awvalid( ctrl_if.awvalid ),
|
||||
.m_axi_awready( ctrl_if.awready ),
|
||||
.m_axi_wdata( ctrl_if.wdata ),
|
||||
.m_axi_wstrb( ctrl_if.wstrb ),
|
||||
.m_axi_wvalid( ctrl_if.wvalid ),
|
||||
.m_axi_wready( ctrl_if.wready ),
|
||||
.m_axi_bresp( ctrl_if.bresp ),
|
||||
.m_axi_bvalid( ctrl_if.bvalid ),
|
||||
.m_axi_bready( ctrl_if.bready ),
|
||||
.m_axi_araddr( ctrl_if.araddr ),
|
||||
.m_axi_arprot( ctrl_if.arprot ),
|
||||
.m_axi_arvalid( ctrl_if.arvalid ),
|
||||
.m_axi_arready( ctrl_if.arready ),
|
||||
.m_axi_rdata( ctrl_if.rdata ),
|
||||
.m_axi_rresp( ctrl_if.rresp ),
|
||||
.m_axi_rvalid( ctrl_if.rvalid ),
|
||||
.m_axi_rready( ctrl_if.rready )
|
||||
|
||||
);
|
||||
|
||||
initial begin
|
||||
vip_mst = new("vip_mst", axi_vip_inst.inst.IF);
|
||||
vip_mst.start_master();
|
||||
end
|
||||
|
||||
wire [127:0] iq_out;
|
||||
wire iq_out_valid;
|
||||
reg start_pulse;
|
||||
|
||||
gen_ofdm dut (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.ctrl_if(ctrl_if),
|
||||
.start_pulse(start_pulse),
|
||||
.iq_out(iq_out),
|
||||
.iq_out_valid(iq_out_valid)
|
||||
);
|
||||
|
||||
int fid_out;
|
||||
|
||||
initial begin
|
||||
reset = 1'b1;
|
||||
clk = 1'b0;
|
||||
start_pulse = 1'b0;
|
||||
$display($time, " << Starting the Simulation >>");
|
||||
|
||||
// Open Output File
|
||||
fid_out = $fopen("/home/bkiedinger/projects/castelion/radar_alinx_kintex/python/waveform_generator/sim_out.bin", "wb");
|
||||
|
||||
// Release Reset
|
||||
repeat(25) @(posedge clk);
|
||||
reset = 1'b0;
|
||||
repeat(25) @(posedge clk);
|
||||
|
||||
// Set Control Regs
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 0, resp);
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 28633115, resp);
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, 0, resp);
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, ('h00010400), resp);
|
||||
|
||||
|
||||
repeat(25) @(posedge clk);
|
||||
start_pulse = 1'b1;
|
||||
@(posedge clk);
|
||||
start_pulse = 1'b0;
|
||||
|
||||
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if ( iq_out_valid == 1'b1 ) begin
|
||||
$fwrite(fid_out, "%d\n", iq_out[15:0] );
|
||||
$fwrite(fid_out, "%d\n", iq_out[31:16]);
|
||||
$fwrite(fid_out, "%d\n", iq_out[47:32]);
|
||||
$fwrite(fid_out, "%d\n", iq_out[63:48]);
|
||||
$fwrite(fid_out, "%d\n", iq_out[79:64]);
|
||||
$fwrite(fid_out, "%d\n", iq_out[95:80]);
|
||||
$fwrite(fid_out, "%d\n", iq_out[111:96]);
|
||||
$fwrite(fid_out, "%d\n", iq_out[127:112]);
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
`resetall
|
||||
@@ -56,20 +56,20 @@
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="34"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="50"/>
|
||||
<Option Name="WTModelSimExportSim" Val="50"/>
|
||||
<Option Name="WTQuestaExportSim" Val="50"/>
|
||||
<Option Name="WTXSimExportSim" Val="53"/>
|
||||
<Option Name="WTModelSimExportSim" Val="53"/>
|
||||
<Option Name="WTQuestaExportSim" Val="53"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="50"/>
|
||||
<Option Name="WTRivieraExportSim" Val="50"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="50"/>
|
||||
<Option Name="WTVcsExportSim" Val="53"/>
|
||||
<Option Name="WTRivieraExportSim" Val="53"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="53"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -517,6 +517,22 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_sine.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_ofdm.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="top"/>
|
||||
@@ -539,11 +555,17 @@
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/sim/tb_gen_ofdm.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="top"/>
|
||||
<Option Name="TopModule" Val="testbench"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
@@ -760,6 +782,36 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="wfg_cordic" Type="BlockSrcs" RelSrcDir="$PSRCDIR/wfg_cordic" RelGenDir="$PGENDIR/wfg_cordic">
|
||||
<File Path="$PSRCDIR/sources_1/ip/wfg_cordic/wfg_cordic.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="wfg_cordic"/>
|
||||
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="axi_vip_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_vip_0" RelGenDir="$PGENDIR/axi_vip_0">
|
||||
<File Path="$PSRCDIR/sources_1/ip/axi_vip_0/axi_vip_0.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="axi_vip_0"/>
|
||||
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@@ -923,6 +975,26 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="wfg_cordic_synth_1" Type="Ft3:Synth" SrcSet="wfg_cordic" Part="xcku040-ffva1156-2-i" ConstrsSet="wfg_cordic" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/wfg_cordic_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wfg_cordic_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wfg_cordic_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_vip_0_synth_1" Type="Ft3:Synth" SrcSet="axi_vip_0" Part="xcku040-ffva1156-2-i" ConstrsSet="axi_vip_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_vip_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_vip_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_vip_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
@@ -1162,6 +1234,40 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="wfg_cordic_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="wfg_cordic" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="wfg_cordic_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wfg_cordic_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wfg_cordic_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_vip_0_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="axi_vip_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_vip_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_vip_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_vip_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="0"/>
|
||||
|
||||
Reference in New Issue
Block a user