bkiedinger@gmail.com 729d034a13 fixed pinout, made some updates for discrete timing pulses, needs to be tested

2025-04-14 08:17:28 -05:00

..

verilog_ethernet

gitting project in git

2025-03-30 21:43:59 -05:00

axi_intf.sv

gitting project in git

2025-03-30 21:43:59 -05:00

axil_slave.v

gitting project in git

2025-03-30 21:43:59 -05:00

digital_rx_chain.v

gitting project in git

2025-03-30 21:43:59 -05:00

ethernet_top.v

gitting project in git

2025-03-30 21:43:59 -05:00

spi.v

gitting project in git

2025-03-30 21:43:59 -05:00

timing_engine.v

fixed pinout, made some updates for discrete timing pulses, needs to be tested

2025-04-14 08:17:28 -05:00

top.v

fixed pinout, made some updates for discrete timing pulses, needs to be tested

2025-04-14 08:17:28 -05:00

util_reg.v

gitting project in git

2025-03-30 21:43:59 -05:00

waveform_gen.v

gitting project in git

2025-03-30 21:43:59 -05:00