bkiedinger b39a2bd54f loop mode works but did not improve data rate

2026-05-25 23:28:02 -05:00

cpp

first commit

2026-05-25 22:36:52 -05:00

project_1.srcs

loop mode works but did not improve data rate

2026-05-25 23:28:02 -05:00

project_1.xpr

loop mode works but did not improve data rate

2026-05-25 23:28:02 -05:00

top.xsa

first commit

2026-05-25 22:36:52 -05:00

S

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15 MiB

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VHDL 90.6%

Verilog 8.9%

SystemVerilog 0.4%