updates to ofdm waveform gen
This commit is contained in:
@@ -2,6 +2,8 @@ from matplotlib import pyplot as plt
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from ctypes import *
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import numpy as np
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from read_data_file import db20n
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def read_sim_output(filename, is_float=False):
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fid = open(filename, "r")
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@@ -24,10 +26,27 @@ def main():
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data[data >= 2**15] -= 2**16
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data = data[0::2] + 1j * data[1::2]
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x = np.fft.fft(data)
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f_axis = np.fft.fftfreq(x.size, d=1/750)
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x = np.fft.fftshift(x)
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f_axis = np.fft.fftshift(f_axis)
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plt.figure()
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plt.plot(f_axis, db20n(x))
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plt.figure()
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plt.plot(data.real)
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plt.plot(data.imag)
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plt.title('Sim Output')
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plt.title('HDL Sim Output - IQ')
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plt.grid()
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plt.figure()
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plt.plot(np.unwrap(np.angle(data)))
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plt.title('HDL Sim Output - Phase')
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plt.grid()
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plt.show()
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@@ -5,10 +5,16 @@ def main():
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f = 10e6
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n = 4096
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start_freq = -20507812.5
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start_freq = start_freq/fs * 2**32
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if (start_freq < 0):
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start_freq += 2**32
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print(start_freq)
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freq = f/fs * 2**31
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delta_freq = 5859375
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delta_freq = delta_freq/fs * 2**32
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print(delta_freq)
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print(freq)
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if __name__ == '__main__':
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main()
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@@ -118,8 +118,8 @@ def wg_ofdm():
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do_agile = False
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n_sub_cpi = 1
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n_tx = 1
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n_rx = 2
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n_pol = 2
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n_rx = 1
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n_pol = 1
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n_samp = 64
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n_samp_chip = 8
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@@ -237,6 +237,7 @@ def wg_ofdm():
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get_pulse_params(n_tx, n_rx, f_samp, n_samp_chip, n_f, n_f_pulse, n_sub_cpi, n_pol, p))
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print(baseband/1e6)
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print(start_phase)
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pulse, _phase = get_waveform(baseband,
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start_phase,
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@@ -247,15 +248,27 @@ def wg_ofdm():
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n_samp * tx_sample_rate_multiplier,
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f_samp * tx_sample_rate_multiplier)
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print('Num Chips', baseband.size)
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print('Start Freq', baseband[0])
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print('Delta Freq', np.unique(np.diff(baseband)))
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pulse = np.squeeze(pulse)
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plt.figure()
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plt.plot(pulse[0, :].real)
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plt.plot(pulse[0, :].imag)
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plt.plot(pulse.real)
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plt.plot(pulse.imag)
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plt.title('Python Output - IQ')
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plt.grid()
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plt.figure()
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plt.plot(pulse[1, :].real)
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plt.plot(pulse[1, :].imag)
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plt.plot(np.unwrap(np.angle(pulse)))
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# plt.plot(np.angle(pulse), '.-')
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plt.title('Python Output - Phase')
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plt.grid()
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# plt.figure()
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# plt.plot(pulse[1, :].real)
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# plt.plot(pulse[1, :].imag)
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plt.show()
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47
python/waveform_generator/wf_ofdm_simple.py
Normal file
47
python/waveform_generator/wf_ofdm_simple.py
Normal file
@@ -0,0 +1,47 @@
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import numpy as np
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from matplotlib import pyplot as plt
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def wg_ofdm():
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tx_sample_rate = 750e6
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rx_decimation = 16
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rx_sample_rate = tx_sample_rate / rx_decimation
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n_rx_samp_per_chip = 16 # Keep at >= x2 of num_chips and start phase will always be 0, if num chips is power of 2?
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num_chips = 8
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n_tx_samp_per_chip = n_rx_samp_per_chip * rx_decimation
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n_tx_samp_per_pulse = n_tx_samp_per_chip * num_chips
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print(n_tx_samp_per_chip / 4)
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chip_freq = (np.arange(num_chips) - num_chips//2 + 0.5)/num_chips * rx_sample_rate
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# First, generate simple in order waveform
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freq = np.repeat(chip_freq, n_tx_samp_per_chip)
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phase = freq / tx_sample_rate
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phase = np.cumsum(np.concatenate([[0], phase]))
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phase = phase[0:-1]
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# Extract the start phases of each chip, ideally these are always 0
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chip_start_phase = phase[0::n_tx_samp_per_chip] % 1
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print(chip_start_phase)
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print(chip_start_phase * 2**16)
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print(chip_freq)
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x = np.exp(1j * 2 * np.pi * phase)
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plt.figure()
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plt.plot(x.real)
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plt.plot(x.imag)
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plt.figure()
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plt.plot(np.unwrap(np.angle(x)))
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plt.show()
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return
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if __name__ == '__main__':
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wg_ofdm()
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28
radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv
Normal file
28
radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv
Normal file
@@ -0,0 +1,28 @@
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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module delay_shift_register #(
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parameter DELAY_CYCLES = 4
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) (
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input wire clk,
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input wire reset,
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input wire data_in,
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output wire data_out
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);
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// Declare a register to hold the shifted data
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reg [DELAY_CYCLES-1:0] shift_reg;
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always @ (posedge clk) begin
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if (reset) begin
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shift_reg <= '0;
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end else begin
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shift_reg <= {shift_reg[DELAY_CYCLES-2:0], data_in};
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end
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end
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assign data_out = shift_reg[DELAY_CYCLES-1];
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endmodule
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`resetall
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@@ -2,6 +2,75 @@
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`timescale 1ns / 1ps
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`default_nettype none
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// Outputs 4 IQ samples in parallel for connection to DAC interface
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// start_pulse - Kicks off output for a single pulse, expected to be a single clock wide
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// start_table_irq - This is used to indicate to software that playback from the top of the sequence table has begin
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// half_table_irq - This is used to indicate to software that playback from the mid point of the sequence table has begin
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// The mid point is defined as (n_total_chips >> 1)
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// These interrupts are used in combination to enable software to continually update the sequence table in a ping pong
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// fashion while the system is operating
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/*
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* ADDR=0x0000 Control Register (reg_ctrl)
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* Currently unused
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*/
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/*
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* ADDR=0x0004 Start Frequency Register (reg_start_freq)
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* Sets the value of the lowest frequency chip, final chip frequincies are calculated using this value,
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* the delta frequency, and the sequence number from the ram
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* Bit 31:0: Frequency
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*/
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/*
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* ADDR=0x0008 Chip Description 0 (reg_chips_0)
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* Bit 15:0: Number of total chips in the sequence table
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*/
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/*
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* ADDR=0x000C Chip Description 1 (reg_chips_1)
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* Bit 15:0: Number of DAC samples per chip divided by 4 (due to parallel output of 4 samples)
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* Bit 31:16: Number of Chips per Pulse
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*/
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/*
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* ADDR=0x0010 Delta Frequency Register (reg_start_freq)
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* Sets the delta frequency value between chips, final chip frequincies are calculated using this value,
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* the delta frequency, and the sequence number from the ram
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* Bit 31:0: Delta Frequency
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*/
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/*
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* ADDR=0x0014 Currently Unused
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*/
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/*
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* ADDR=0x0018 Sequence Memory Write Address
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* Sets the write address of the sequence memory
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* Bit 15:0: BRAM Write Address
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*/
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/*
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* ADDR=0x001C Sequence Memory Write Data
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* Write a value into the sequence BRAM, and automatically increments the address.
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* Repeated writes to this registers store values in sequential address in the BRAM
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* Bit 15:0: BRAM Write Data
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*/
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/*
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* ADDR=0x0020 Start Phase Memory Write Address
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* Sets the write address of the sequence memory
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* Bit 15:0: BRAM Write Address
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*/
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/*
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* ADDR=0x0024 Start Phase Memory Write Data
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* Write a value into the sequence BRAM, and automatically increments the address.
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* Repeated writes to this registers store values in sequential address in the BRAM
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* Bit 15:0: BRAM Write Data
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*/
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module gen_ofdm # (
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parameter integer AXI_ADDR_WIDTH = 32,
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parameter integer AXI_DATA_WIDTH = 32
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@@ -13,10 +82,50 @@ module gen_ofdm # (
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input wire start_pulse,
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output wire start_table_irq,
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output wire half_table_irq,
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output wire [127:0] iq_out,
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output wire iq_out_valid
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);
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// ------------------------------
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// BRAM for holding sequence
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// ------------------------------
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wire [15:0] read_addr;
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wire [15:0] read_sequence;
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reg bram_we;
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reg [15:0] bram_waddr;
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reg [15:0] bram_wdata;
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ofdm_sequence_ram sequence_ram (
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.clka(ctrl_if.clk),
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.ena(1'b1),
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.wea(bram_we),
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.addra(bram_waddr),
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.dina(bram_wdata),
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.clkb(clk),
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.enb(1'b1),
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.addrb(read_addr),
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.doutb(read_sequence)
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);
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wire [15:0] read_phase;
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reg phase_bram_we;
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reg [15:0] phase_bram_waddr;
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reg [15:0] phase_bram_wdata;
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ofdm_sequence_ram phase_ram (
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.clka(ctrl_if.clk),
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.ena(1'b1),
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.wea(phase_bram_we),
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.addra(phase_bram_waddr),
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.dina(phase_bram_wdata),
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.clkb(clk),
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.enb(1'b1),
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.addrb(read_addr),
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.doutb(read_phase)
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);
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// ------------------------------
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// AXIL Decode
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// ------------------------------
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@@ -69,39 +178,79 @@ axil_slave
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// Config Registers
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// ------------------------------
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reg [31:0] reg_ctrl;
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reg [31:0] reg_freq;
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reg [31:0] reg_phase;
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reg [31:0] reg_chips;
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reg [31:0] reg_start_freq;
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reg [31:0] reg_delta_freq;
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reg [31:0] reg_delta_phase;
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reg [31:0] reg_chips_0;
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reg [31:0] reg_chips_1;
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always @ (posedge ctrl_if.clk) begin
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if (~ctrl_if.resetn) begin
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reg_ctrl <= 0;
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reg_freq <= 0;
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reg_phase <= 0;
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reg_start_freq <= 0;
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reg_delta_freq <= 0;
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reg_chips_0 <= 0;
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reg_chips_1 <= 0;
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reg_delta_phase <= 0;
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bram_we <= 1'b0;
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bram_waddr <= 0;
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bram_wdata <= 0;
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phase_bram_we <= 1'b0;
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phase_bram_waddr <= 0;
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phase_bram_wdata <= 0;
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end else begin
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bram_we <= 1'b0;
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if (bram_we) begin
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bram_waddr <= bram_waddr + 1;
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end
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phase_bram_we <= 1'b0;
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if (phase_bram_we) begin
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phase_bram_waddr <= phase_bram_waddr + 1;
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end
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if (wren) begin
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if (waddr[11:0] == 'h000) begin
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reg_ctrl <= wdata;
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end
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if (waddr[11:0] == 'h004) begin
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reg_freq <= wdata;
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reg_start_freq <= wdata;
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end
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if (waddr[11:0] == 'h008) begin
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reg_phase <= wdata;
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reg_chips_0 <= wdata;
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end
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if (waddr[11:0] == 'h00C) begin
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reg_chips <= wdata;
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reg_chips_1 <= wdata;
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end
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// if (waddr[11:0] == 'h010) begin
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// reg_phase <= wdata;
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// end
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if (waddr[11:0] == 'h010) begin
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reg_delta_freq <= wdata;
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end
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if (waddr[11:0] == 'h014) begin
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reg_delta_phase <= wdata;
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end
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if (waddr[11:0] == 'h018) begin
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bram_waddr <= wdata;
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end
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if (waddr[11:0] == 'h01C) begin
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bram_we <= 1'b1;
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bram_wdata <= wdata;
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end
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if (waddr[11:0] == 'h020) begin
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phase_bram_waddr <= wdata;
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end
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if (waddr[11:0] == 'h024) begin
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phase_bram_we <= 1'b1;
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phase_bram_wdata <= wdata;
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end
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end
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end
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end
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wire [15:0] n_samp_chip = reg_chips[15:0];
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wire [15:0] n_chip = reg_chips[31:16];
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wire [15:0] n_total_chips = reg_chips_0[15:0];
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wire [15:0] n_samp_per_chip = reg_chips_1[15:0];
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wire [15:0] n_chip_per_pulse = reg_chips_1[31:16];
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// ------------------------------
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// Bla
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@@ -109,47 +258,116 @@ wire [15:0] n_chip = reg_chips[31:16];
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reg [24:0] pulse_cnt;
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reg [15:0] chip_cnt;
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reg [15:0] chip_ind;
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reg [15:0] chip_per_pulse_cnt;
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reg pulse_active;
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reg start_of_pulse;
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wire set_phase;
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reg start_irq;
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reg half_irq;
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assign read_addr = chip_ind;
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assign start_table_irq = start_irq;
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assign half_table_irq = half_irq;
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always @ (posedge clk) begin
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if (reset) begin
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chip_cnt <= 0;
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chip_ind <= 0;
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chip_per_pulse_cnt <= 0;
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pulse_active <= 1'b0;
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start_of_pulse <= 1'b0;
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end else begin
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start_of_pulse <= 1'b0;
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if (start_pulse) begin
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chip_cnt <= 0;
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chip_ind <= 0;
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chip_per_pulse_cnt <= 0;
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pulse_active <= 1'b1;
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start_of_pulse <= 1'b1;
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end
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if (pulse_active) begin
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chip_cnt <= chip_cnt + 1;
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if (chip_cnt == n_samp_chip - 1) begin
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if (chip_cnt == n_samp_per_chip - 1) begin
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chip_cnt <= 0;
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chip_ind <= chip_ind + 1;
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if (chip_ind == n_chip - 1) begin
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chip_ind <= 0;
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pulse_active = 1'b0;
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chip_per_pulse_cnt <= chip_per_pulse_cnt + 1;
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if (chip_per_pulse_cnt == n_chip_per_pulse - 1) begin
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chip_per_pulse_cnt <= 0;
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pulse_active <= 1'b0;
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if (chip_ind == n_total_chips-1) begin
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chip_ind <= 0;
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end
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end
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end
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end
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start_irq <= 1'b0;
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if (pulse_active) begin
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if (chip_cnt == 0) begin
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if (chip_ind == 0) begin
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start_irq <= 1'b1;
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end
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end
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end
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half_irq <= 1'b0;
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if (pulse_active) begin
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if (chip_cnt == 0) begin
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if (chip_ind == (n_total_chips >> 1)) begin
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half_irq <= 1'b1;
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end
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end
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end
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end
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end
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wire [47:0] mult_out;
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wire [31:0] chip_delta_freq;
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ofdm_freq_mult freq_mult (
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.CLK(clk),
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.A(reg_delta_freq),
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.B(read_sequence),
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.P(mult_out)
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);
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assign chip_delta_freq = mult_out[31:0];
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reg [31:0] chip_freq;
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reg [15:0] read_phase_q;
|
||||
reg [15:0] read_phase_q2;
|
||||
always @ (posedge clk) begin
|
||||
chip_freq <= chip_delta_freq + reg_start_freq;
|
||||
read_phase_q <= read_phase;
|
||||
read_phase_q2 <= read_phase_q;
|
||||
end
|
||||
|
||||
assign set_phase = (chip_cnt == 0) ? pulse_active : 1'b0;
|
||||
|
||||
wire pulse_active_delayed;
|
||||
delay_shift_register # (
|
||||
.DELAY_CYCLES(4)
|
||||
) delay_valid (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.data_in(pulse_active),
|
||||
.data_out(pulse_active_delayed)
|
||||
);
|
||||
|
||||
wire set_phase_delayed;
|
||||
delay_shift_register # (
|
||||
.DELAY_CYCLES(4)
|
||||
) delay_set_phase (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.data_in(set_phase),
|
||||
.data_out(set_phase_delayed)
|
||||
);
|
||||
|
||||
|
||||
gen_sine gen_sine_i (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.set_phase(start_of_pulse),
|
||||
.valid(pulse_active),
|
||||
.phase(reg_phase),
|
||||
.frequency(reg_freq),
|
||||
.set_phase(set_phase_delayed),
|
||||
.valid(pulse_active_delayed),
|
||||
.phase({read_phase_q2, 16'h0000}),
|
||||
.frequency(chip_freq),
|
||||
.iq_out(iq_out),
|
||||
.iq_out_valid(iq_out_valid)
|
||||
);
|
||||
|
||||
@@ -0,0 +1,160 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ofdm_freq_mult",
|
||||
"component_reference": "xilinx.com:ip:mult_gen:12.0",
|
||||
"ip_revision": "18",
|
||||
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/ofdm_freq_mult",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ofdm_freq_mult", "resolve_type": "user", "usage": "all" } ],
|
||||
"MultType": [ { "value": "Parallel_Multiplier", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAWidth": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PortBType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortBWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ConstValue": [ { "value": "129", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"CcmImp": [ { "value": "Distributed_Memory", "resolve_type": "user", "usage": "all" } ],
|
||||
"Multiplier_Construction": [ { "value": "Use_Mults", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"OptGoal": [ { "value": "Speed", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Custom_Output_Width": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OutputWidthHigh": [ { "value": "47", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"OutputWidthLow": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"UseRounding": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RoundPoint": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PipeStages": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"ClockEnable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SyncClear": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SclrCePriority": [ { "value": "SCLR_Overrides_CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"ZeroDetect": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MODEL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_GOAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_HIGH": [ { "value": "47", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MULT_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CCM_IMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_VALUE": [ { "value": "10000001", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ZERO_DETECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_PT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "kintexu" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcku040" } ],
|
||||
"PACKAGE": [ { "value": "ffva1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "18" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/ofdm_freq_mult" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"A": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"B": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"P": [ { "direction": "out", "size_left": "47", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"a_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
}
|
||||
},
|
||||
"clk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "p_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"b_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "B" } ]
|
||||
}
|
||||
},
|
||||
"p_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,281 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ofdm_sequence_ram",
|
||||
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
|
||||
"ip_revision": "5",
|
||||
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/ofdm_sequence_ram",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "ofdm_sequence_ram", "resolve_type": "user", "usage": "all" } ],
|
||||
"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "Simple_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "usage": "all" } ],
|
||||
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
|
||||
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Width_A": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Write_Depth_A": [ { "value": "65536", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Read_Width_A": [ { "value": "16", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Operating_Mode_A": [ { "value": "NO_CHANGE", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Width_B": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Read_Width_B": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_B": [ { "value": "Use_ENB_Pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
|
||||
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
|
||||
"CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
|
||||
"EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INIT_FILE": [ { "value": "ofdm_sequence_ram.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_A": [ { "value": "NO_CHANGE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_A": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_A": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_A": [ { "value": "65536", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_A": [ { "value": "65536", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_B": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_B": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_B": [ { "value": "65536", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_B": [ { "value": "65536", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRB_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_36K_BRAM": [ { "value": "30", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 67.737392 mW", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "kintexu" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcku040" } ],
|
||||
"PACKAGE": [ { "value": "ffva1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "5" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/ofdm_sequence_ram" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"ena": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"addra": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"dina": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"clkb": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"enb": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"addrb": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"doutb": [ { "direction": "out", "size_left": "15", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"RST.ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DIN": [ { "physical_name": "dina" } ],
|
||||
"EN": [ { "physical_name": "ena" } ],
|
||||
"WE": [ { "physical_name": "wea" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTB": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addrb" } ],
|
||||
"CLK": [ { "physical_name": "clkb" } ],
|
||||
"DOUT": [ { "physical_name": "doutb" } ],
|
||||
"EN": [ { "physical_name": "enb" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -73,6 +73,11 @@ gen_ofdm dut (
|
||||
|
||||
int fid_out;
|
||||
|
||||
reg [15:0] n_samp_per_chip;
|
||||
reg [15:0] n_chip_per_pulse;
|
||||
reg [15:0] n_total_chips;
|
||||
reg [15:0] n_pulses;
|
||||
|
||||
initial begin
|
||||
reset = 1'b1;
|
||||
clk = 1'b0;
|
||||
@@ -87,21 +92,52 @@ initial begin
|
||||
reset = 1'b0;
|
||||
repeat(25) @(posedge clk);
|
||||
|
||||
n_samp_per_chip = 64;
|
||||
n_chip_per_pulse = 8;
|
||||
n_total_chips = 16;
|
||||
n_pulses = 4;
|
||||
|
||||
|
||||
// Set Control Regs
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 0, resp);
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 28633115, resp);
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, 0, resp);
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, ('h00010400), resp);
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 4177526784, resp); // Start Freq
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, n_total_chips, resp);
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, (n_chip_per_pulse << 16) | n_samp_per_chip, resp);
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h0010, 0, 33554432, resp); // Delta Freq
|
||||
|
||||
// Load Sequence
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h0018, 0, 0, resp); // Set Start Address
|
||||
for (int i = 0; i < 8; i = i + 1) begin
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h001C, 0, i, resp); // Load Chirp Sequence
|
||||
end
|
||||
for (int i = 0; i < 8; i = i + 1) begin
|
||||
vip_mst.AXI4LITE_WRITE_BURST(16'h001C, 0, i, resp); // Load Chirp Sequence
|
||||
end
|
||||
|
||||
// Load Start Phases
|
||||
// vip_mst.AXI4LITE_WRITE_BURST(16'h0020, 0, 0, resp); // Set Start Address
|
||||
// for (int i = 0; i < 8; i = i + 1) begin
|
||||
// vip_mst.AXI4LITE_WRITE_BURST(16'h0024, 0, i, resp); // Load Chirp Sequence
|
||||
// end
|
||||
|
||||
for (int i = 0; i < n_pulses; i = i + 1) begin
|
||||
|
||||
repeat(1000) @(posedge clk);
|
||||
start_pulse = 1'b1;
|
||||
@(posedge clk);
|
||||
start_pulse = 1'b0;
|
||||
|
||||
repeat(n_samp_per_chip * n_chip_per_pulse) @(posedge clk);
|
||||
end
|
||||
|
||||
|
||||
repeat(25) @(posedge clk);
|
||||
start_pulse = 1'b1;
|
||||
@(posedge clk);
|
||||
start_pulse = 1'b0;
|
||||
|
||||
repeat(10000) @(posedge clk);
|
||||
$fclose(fid_out);
|
||||
$display($time, " << Ending the Simulation >>");
|
||||
$stop;
|
||||
|
||||
end
|
||||
|
||||
// Write output data to file
|
||||
always @ (posedge clk) begin
|
||||
if ( iq_out_valid == 1'b1 ) begin
|
||||
$fwrite(fid_out, "%d\n", iq_out[15:0] );
|
||||
|
||||
@@ -56,20 +56,20 @@
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="34"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="82"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="53"/>
|
||||
<Option Name="WTModelSimExportSim" Val="53"/>
|
||||
<Option Name="WTQuestaExportSim" Val="53"/>
|
||||
<Option Name="WTXSimExportSim" Val="55"/>
|
||||
<Option Name="WTModelSimExportSim" Val="55"/>
|
||||
<Option Name="WTQuestaExportSim" Val="55"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="53"/>
|
||||
<Option Name="WTRivieraExportSim" Val="53"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="53"/>
|
||||
<Option Name="WTVcsExportSim" Val="55"/>
|
||||
<Option Name="WTRivieraExportSim" Val="55"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="55"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -533,6 +533,14 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/hdl/delay_shift_reg.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="top"/>
|
||||
@@ -812,6 +820,36 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="ofdm_sequence_ram" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ofdm_sequence_ram" RelGenDir="$PGENDIR/ofdm_sequence_ram">
|
||||
<File Path="$PSRCDIR/sources_1/ip/ofdm_sequence_ram/ofdm_sequence_ram.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="ofdm_sequence_ram"/>
|
||||
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="ofdm_freq_mult" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ofdm_freq_mult" RelGenDir="$PGENDIR/ofdm_freq_mult">
|
||||
<File Path="$PSRCDIR/sources_1/ip/ofdm_freq_mult/ofdm_freq_mult.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="ofdm_freq_mult"/>
|
||||
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@@ -995,6 +1033,26 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ofdm_sequence_ram_synth_1" Type="Ft3:Synth" SrcSet="ofdm_sequence_ram" Part="xcku040-ffva1156-2-i" ConstrsSet="ofdm_sequence_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ofdm_sequence_ram_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ofdm_freq_mult_synth_1" Type="Ft3:Synth" SrcSet="ofdm_freq_mult" Part="xcku040-ffva1156-2-i" ConstrsSet="ofdm_freq_mult" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ofdm_freq_mult_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ofdm_freq_mult_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ofdm_freq_mult_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
@@ -1268,6 +1326,40 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ofdm_sequence_ram_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="ofdm_sequence_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ofdm_sequence_ram_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ofdm_freq_mult_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="ofdm_freq_mult" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ofdm_freq_mult_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ofdm_freq_mult_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ofdm_freq_mult_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="0"/>
|
||||
|
||||
Reference in New Issue
Block a user