updates to ofdm waveform gen
This commit is contained in:
28
radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv
Normal file
28
radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv
Normal file
@@ -0,0 +1,28 @@
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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module delay_shift_register #(
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parameter DELAY_CYCLES = 4
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) (
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input wire clk,
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input wire reset,
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input wire data_in,
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output wire data_out
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);
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// Declare a register to hold the shifted data
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reg [DELAY_CYCLES-1:0] shift_reg;
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always @ (posedge clk) begin
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if (reset) begin
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shift_reg <= '0;
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end else begin
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shift_reg <= {shift_reg[DELAY_CYCLES-2:0], data_in};
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end
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end
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assign data_out = shift_reg[DELAY_CYCLES-1];
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endmodule
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`resetall
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@@ -2,6 +2,75 @@
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`timescale 1ns / 1ps
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`default_nettype none
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// Outputs 4 IQ samples in parallel for connection to DAC interface
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// start_pulse - Kicks off output for a single pulse, expected to be a single clock wide
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// start_table_irq - This is used to indicate to software that playback from the top of the sequence table has begin
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// half_table_irq - This is used to indicate to software that playback from the mid point of the sequence table has begin
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// The mid point is defined as (n_total_chips >> 1)
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// These interrupts are used in combination to enable software to continually update the sequence table in a ping pong
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// fashion while the system is operating
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/*
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* ADDR=0x0000 Control Register (reg_ctrl)
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* Currently unused
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*/
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/*
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* ADDR=0x0004 Start Frequency Register (reg_start_freq)
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* Sets the value of the lowest frequency chip, final chip frequincies are calculated using this value,
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* the delta frequency, and the sequence number from the ram
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* Bit 31:0: Frequency
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*/
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/*
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* ADDR=0x0008 Chip Description 0 (reg_chips_0)
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* Bit 15:0: Number of total chips in the sequence table
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*/
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/*
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* ADDR=0x000C Chip Description 1 (reg_chips_1)
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* Bit 15:0: Number of DAC samples per chip divided by 4 (due to parallel output of 4 samples)
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* Bit 31:16: Number of Chips per Pulse
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*/
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/*
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* ADDR=0x0010 Delta Frequency Register (reg_start_freq)
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* Sets the delta frequency value between chips, final chip frequincies are calculated using this value,
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* the delta frequency, and the sequence number from the ram
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* Bit 31:0: Delta Frequency
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*/
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/*
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* ADDR=0x0014 Currently Unused
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*/
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/*
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* ADDR=0x0018 Sequence Memory Write Address
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* Sets the write address of the sequence memory
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* Bit 15:0: BRAM Write Address
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*/
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/*
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* ADDR=0x001C Sequence Memory Write Data
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* Write a value into the sequence BRAM, and automatically increments the address.
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* Repeated writes to this registers store values in sequential address in the BRAM
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* Bit 15:0: BRAM Write Data
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*/
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/*
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* ADDR=0x0020 Start Phase Memory Write Address
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* Sets the write address of the sequence memory
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* Bit 15:0: BRAM Write Address
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*/
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/*
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* ADDR=0x0024 Start Phase Memory Write Data
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* Write a value into the sequence BRAM, and automatically increments the address.
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* Repeated writes to this registers store values in sequential address in the BRAM
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* Bit 15:0: BRAM Write Data
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*/
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module gen_ofdm # (
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parameter integer AXI_ADDR_WIDTH = 32,
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parameter integer AXI_DATA_WIDTH = 32
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@@ -13,10 +82,50 @@ module gen_ofdm # (
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input wire start_pulse,
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output wire start_table_irq,
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output wire half_table_irq,
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output wire [127:0] iq_out,
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output wire iq_out_valid
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);
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// ------------------------------
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// BRAM for holding sequence
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// ------------------------------
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wire [15:0] read_addr;
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wire [15:0] read_sequence;
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reg bram_we;
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reg [15:0] bram_waddr;
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reg [15:0] bram_wdata;
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ofdm_sequence_ram sequence_ram (
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.clka(ctrl_if.clk),
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.ena(1'b1),
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.wea(bram_we),
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.addra(bram_waddr),
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.dina(bram_wdata),
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.clkb(clk),
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.enb(1'b1),
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.addrb(read_addr),
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.doutb(read_sequence)
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);
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wire [15:0] read_phase;
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reg phase_bram_we;
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reg [15:0] phase_bram_waddr;
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reg [15:0] phase_bram_wdata;
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ofdm_sequence_ram phase_ram (
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.clka(ctrl_if.clk),
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.ena(1'b1),
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.wea(phase_bram_we),
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.addra(phase_bram_waddr),
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.dina(phase_bram_wdata),
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.clkb(clk),
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.enb(1'b1),
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.addrb(read_addr),
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.doutb(read_phase)
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);
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// ------------------------------
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// AXIL Decode
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// ------------------------------
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@@ -69,39 +178,79 @@ axil_slave
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// Config Registers
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// ------------------------------
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reg [31:0] reg_ctrl;
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reg [31:0] reg_freq;
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reg [31:0] reg_phase;
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reg [31:0] reg_chips;
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reg [31:0] reg_start_freq;
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reg [31:0] reg_delta_freq;
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reg [31:0] reg_delta_phase;
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reg [31:0] reg_chips_0;
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reg [31:0] reg_chips_1;
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always @ (posedge ctrl_if.clk) begin
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if (~ctrl_if.resetn) begin
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reg_ctrl <= 0;
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reg_freq <= 0;
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reg_phase <= 0;
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reg_start_freq <= 0;
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reg_delta_freq <= 0;
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reg_chips_0 <= 0;
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reg_chips_1 <= 0;
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reg_delta_phase <= 0;
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bram_we <= 1'b0;
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bram_waddr <= 0;
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bram_wdata <= 0;
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phase_bram_we <= 1'b0;
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phase_bram_waddr <= 0;
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phase_bram_wdata <= 0;
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end else begin
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bram_we <= 1'b0;
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if (bram_we) begin
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bram_waddr <= bram_waddr + 1;
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end
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phase_bram_we <= 1'b0;
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if (phase_bram_we) begin
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phase_bram_waddr <= phase_bram_waddr + 1;
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end
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if (wren) begin
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if (waddr[11:0] == 'h000) begin
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reg_ctrl <= wdata;
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end
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if (waddr[11:0] == 'h004) begin
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reg_freq <= wdata;
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reg_start_freq <= wdata;
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end
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if (waddr[11:0] == 'h008) begin
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reg_phase <= wdata;
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reg_chips_0 <= wdata;
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end
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if (waddr[11:0] == 'h00C) begin
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reg_chips <= wdata;
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reg_chips_1 <= wdata;
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end
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// if (waddr[11:0] == 'h010) begin
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// reg_phase <= wdata;
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// end
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if (waddr[11:0] == 'h010) begin
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reg_delta_freq <= wdata;
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end
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if (waddr[11:0] == 'h014) begin
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reg_delta_phase <= wdata;
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end
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if (waddr[11:0] == 'h018) begin
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bram_waddr <= wdata;
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end
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if (waddr[11:0] == 'h01C) begin
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bram_we <= 1'b1;
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bram_wdata <= wdata;
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end
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if (waddr[11:0] == 'h020) begin
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phase_bram_waddr <= wdata;
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end
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if (waddr[11:0] == 'h024) begin
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phase_bram_we <= 1'b1;
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phase_bram_wdata <= wdata;
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end
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end
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end
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end
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wire [15:0] n_samp_chip = reg_chips[15:0];
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wire [15:0] n_chip = reg_chips[31:16];
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wire [15:0] n_total_chips = reg_chips_0[15:0];
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wire [15:0] n_samp_per_chip = reg_chips_1[15:0];
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wire [15:0] n_chip_per_pulse = reg_chips_1[31:16];
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// ------------------------------
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// Bla
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@@ -109,47 +258,116 @@ wire [15:0] n_chip = reg_chips[31:16];
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reg [24:0] pulse_cnt;
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reg [15:0] chip_cnt;
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reg [15:0] chip_ind;
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reg [15:0] chip_per_pulse_cnt;
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reg pulse_active;
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reg start_of_pulse;
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wire set_phase;
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reg start_irq;
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reg half_irq;
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assign read_addr = chip_ind;
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assign start_table_irq = start_irq;
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assign half_table_irq = half_irq;
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always @ (posedge clk) begin
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if (reset) begin
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chip_cnt <= 0;
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chip_ind <= 0;
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chip_per_pulse_cnt <= 0;
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pulse_active <= 1'b0;
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start_of_pulse <= 1'b0;
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end else begin
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start_of_pulse <= 1'b0;
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if (start_pulse) begin
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chip_cnt <= 0;
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chip_ind <= 0;
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chip_per_pulse_cnt <= 0;
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pulse_active <= 1'b1;
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start_of_pulse <= 1'b1;
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end
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if (pulse_active) begin
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chip_cnt <= chip_cnt + 1;
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if (chip_cnt == n_samp_chip - 1) begin
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if (chip_cnt == n_samp_per_chip - 1) begin
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chip_cnt <= 0;
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chip_ind <= chip_ind + 1;
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if (chip_ind == n_chip - 1) begin
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chip_ind <= 0;
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pulse_active = 1'b0;
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chip_per_pulse_cnt <= chip_per_pulse_cnt + 1;
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if (chip_per_pulse_cnt == n_chip_per_pulse - 1) begin
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chip_per_pulse_cnt <= 0;
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pulse_active <= 1'b0;
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if (chip_ind == n_total_chips-1) begin
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chip_ind <= 0;
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end
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end
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end
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end
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start_irq <= 1'b0;
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if (pulse_active) begin
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if (chip_cnt == 0) begin
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if (chip_ind == 0) begin
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start_irq <= 1'b1;
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end
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end
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end
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half_irq <= 1'b0;
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if (pulse_active) begin
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if (chip_cnt == 0) begin
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if (chip_ind == (n_total_chips >> 1)) begin
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half_irq <= 1'b1;
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end
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end
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end
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end
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end
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wire [47:0] mult_out;
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wire [31:0] chip_delta_freq;
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ofdm_freq_mult freq_mult (
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.CLK(clk),
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.A(reg_delta_freq),
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.B(read_sequence),
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.P(mult_out)
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);
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assign chip_delta_freq = mult_out[31:0];
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reg [31:0] chip_freq;
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reg [15:0] read_phase_q;
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reg [15:0] read_phase_q2;
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always @ (posedge clk) begin
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chip_freq <= chip_delta_freq + reg_start_freq;
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read_phase_q <= read_phase;
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read_phase_q2 <= read_phase_q;
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end
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assign set_phase = (chip_cnt == 0) ? pulse_active : 1'b0;
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wire pulse_active_delayed;
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delay_shift_register # (
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.DELAY_CYCLES(4)
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) delay_valid (
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.clk(clk),
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.reset(reset),
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.data_in(pulse_active),
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.data_out(pulse_active_delayed)
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);
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wire set_phase_delayed;
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delay_shift_register # (
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.DELAY_CYCLES(4)
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) delay_set_phase (
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.clk(clk),
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.reset(reset),
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.data_in(set_phase),
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.data_out(set_phase_delayed)
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);
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gen_sine gen_sine_i (
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.clk(clk),
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.reset(reset),
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.set_phase(start_of_pulse),
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.valid(pulse_active),
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.phase(reg_phase),
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.frequency(reg_freq),
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.set_phase(set_phase_delayed),
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.valid(pulse_active_delayed),
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.phase({read_phase_q2, 16'h0000}),
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.frequency(chip_freq),
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.iq_out(iq_out),
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.iq_out_valid(iq_out_valid)
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);
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