bkiedinger/castelion_radar_alinx_kintex
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updates to ofdm waveform gen

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bkiedinger@gmail.com
2025-10-17 11:52:35 -05:00
parent 086c5dd9f3
commit 60ac0021c8
10 changed files with 951 additions and 51 deletions
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54
radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv
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@@ -73,6 +73,11 @@ gen_ofdm dut (
int fid_out;
reg [15:0] n_samp_per_chip;
reg [15:0] n_chip_per_pulse;
reg [15:0] n_total_chips;
reg [15:0] n_pulses;
initial begin
reset = 1'b1;
clk = 1'b0;
@@ -87,21 +92,52 @@ initial begin
reset = 1'b0;
repeat(25) @(posedge clk);
n_samp_per_chip = 64;
n_chip_per_pulse = 8;
n_total_chips = 16;
n_pulses = 4;
// Set Control Regs
vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 0, resp);
vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 28633115, resp);
vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, 0, resp);
vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, ('h00010400), resp);
vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 4177526784, resp); // Start Freq
vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, n_total_chips, resp);
vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, (n_chip_per_pulse << 16) | n_samp_per_chip, resp);
vip_mst.AXI4LITE_WRITE_BURST(16'h0010, 0, 33554432, resp); // Delta Freq
// Load Sequence
vip_mst.AXI4LITE_WRITE_BURST(16'h0018, 0, 0, resp); // Set Start Address
for (int i = 0; i < 8; i = i + 1) begin
vip_mst.AXI4LITE_WRITE_BURST(16'h001C, 0, i, resp); // Load Chirp Sequence
end
for (int i = 0; i < 8; i = i + 1) begin
vip_mst.AXI4LITE_WRITE_BURST(16'h001C, 0, i, resp); // Load Chirp Sequence
end
// Load Start Phases
// vip_mst.AXI4LITE_WRITE_BURST(16'h0020, 0, 0, resp); // Set Start Address
// for (int i = 0; i < 8; i = i + 1) begin
// vip_mst.AXI4LITE_WRITE_BURST(16'h0024, 0, i, resp); // Load Chirp Sequence
// end
for (int i = 0; i < n_pulses; i = i + 1) begin
repeat(1000) @(posedge clk);
start_pulse = 1'b1;
@(posedge clk);
start_pulse = 1'b0;
repeat(n_samp_per_chip * n_chip_per_pulse) @(posedge clk);
end
repeat(25) @(posedge clk);
start_pulse = 1'b1;
@(posedge clk);
start_pulse = 1'b0;
repeat(10000) @(posedge clk);
$fclose(fid_out);
$display($time, " << Ending the Simulation >>");
$stop;
end
// Write output data to file
always @ (posedge clk) begin
if ( iq_out_valid == 1'b1 ) begin
$fwrite(fid_out, "%d\n", iq_out[15:0] );