bkiedinger/castelion_radar_alinx_kintex
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this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

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bkiedinger@gmail.com
2025-04-25 06:26:07 -05:00
parent 729d034a13
commit 8a1a6ea770
30 changed files with 22794 additions and 22500 deletions
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3
python/data_recorder.py
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@@ -122,6 +122,9 @@ class DataRecorder:
self.write_queue.put(n)
offset += n
if offset >= len(self.buffer):
if self.port == 1234:
print('hmmm', n, offset, len(self.buffer))
offset = offset % len(self.buffer)
# print(offset)

14
python/radar_manager.py
View File

@@ -253,16 +253,20 @@ class RadarManager:
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x8, start_sample >> 2)
# Setup RX Strobe
self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, start_sample)
self.axi_write_register(TIMING_ENGINE_ADDR + 0x8C + i * 8, num_samples)
# self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, start_sample >> 2)
# self.axi_write_register(TIMING_ENGINE_ADDR + 0x8C + i * 8, num_samples >> 2)
# Just force the enable high all the time before we start running
self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, 0x1FFFFFFF)
def setup_tx(self, num_samples, start_sample):
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x4, num_samples >> 2)
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x8, start_sample >> 2)
# Setup TX Strobe
self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, start_sample)
self.axi_write_register(TIMING_ENGINE_ADDR + 0x84, num_samples)
# self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, start_sample >> 2)
# self.axi_write_register(TIMING_ENGINE_ADDR + 0x84, num_samples >> 2)
# Just force the enable high all the time before we start running
self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, 0x1FFFFFFF)
def start_running(self):
for i in range(NUM_RX):
@@ -274,7 +278,9 @@ class RadarManager:
self.axi_write_register(TIMING_ENGINE_ADDR + 0x0, 1) # Timing Engine Reset
for i in range(NUM_RX):
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x0, 1) # RX Reset
self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, 0x0FFFFFF) # Clear RX Enable
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x0, 1) # TX Reset
self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, 0x0FFFFFF) # Clear TX Enable
def setup_rf_attenuators(self, rf_atten):
self.rf_spi_write((1 << 0), 6, rf_atten[0]) # TX0 RF (ADRF5730)