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this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

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This commit is contained in:
bkiedinger@gmail.com
2025-04-25 06:26:07 -05:00
parent 729d034a13
commit 8a1a6ea770
30 changed files with 22794 additions and 22500 deletions
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187
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
View File

@@ -11,6 +11,7 @@ set_property CFGBVS VCCO [current_design]
#-------------------------------------------
set_false_path -from [get_cells util_reg_i/reg_*]
set_false_path -from [get_cells timing_engine_i/reg_*]
set_false_path -from [get_cells timing_engine_i/genblk1*reg_*]
set_false_path -from [get_cells timing_engine_i/system_time_start_of_cpi*]
set_false_path -from [get_cells *digital_rx_chain_i/reg_*]
set_false_path -from [get_cells waveform_gen_i/reg_*]
@@ -32,32 +33,67 @@ set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_200_n]
# set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_p]
# set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_n]
#-------------------------------------------
# I2C
#-------------------------------------------
set_property PACKAGE_PIN P24 [get_ports i2c_scl]
set_property PACKAGE_PIN P25 [get_ports i2c_sda]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda]
#-------------------------------------------
# RF Attenautors
#-------------------------------------------
set_property PACKAGE_PIN G25 [get_ports tx0_rf_attn_sin]
set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk]
set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le]
set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin]
set_property PACKAGE_PIN P23 [get_ports tx1_rf_attn_clk]
set_property PACKAGE_PIN R23 [get_ports tx1_rf_attn_le]
set_property PACKAGE_PIN K25 [get_ports txlo_drv_en]
# FMC2
#set_property PACKAGE_PIN G25 [get_ports tx0_rf_attn_sin]
#set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk]
#set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le]
#set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin]
#set_property PACKAGE_PIN P23 [get_ports tx1_rf_attn_clk]
#set_property PACKAGE_PIN R23 [get_ports tx1_rf_attn_le]
#set_property PACKAGE_PIN K25 [get_ports txlo_drv_en]
set_property PACKAGE_PIN R25 [get_ports rx0_rf_attn_sin]
set_property PACKAGE_PIN T25 [get_ports rx0_rf_attn_clk]
set_property PACKAGE_PIN T24 [get_ports rx0_rf_attn_le]
set_property PACKAGE_PIN AM11 [get_ports rx0_if_attn_sin]
set_property PACKAGE_PIN AF13 [get_ports rx0_if_attn_clk]
set_property PACKAGE_PIN AE13 [get_ports rx0_if_attn_le]
set_property PACKAGE_PIN AN11 [get_ports rx0_lna_en]
#set_property PACKAGE_PIN R25 [get_ports rx0_rf_attn_sin]
#set_property PACKAGE_PIN T25 [get_ports rx0_rf_attn_clk]
#set_property PACKAGE_PIN T24 [get_ports rx0_rf_attn_le]
#set_property PACKAGE_PIN AM11 [get_ports rx0_if_attn_sin]
#set_property PACKAGE_PIN AF13 [get_ports rx0_if_attn_clk]
#set_property PACKAGE_PIN AE13 [get_ports rx0_if_attn_le]
#set_property PACKAGE_PIN AN11 [get_ports rx0_lna_en]
set_property PACKAGE_PIN J24 [get_ports rx1_rf_attn_sin]
set_property PACKAGE_PIN G27 [get_ports rx1_rf_attn_clk]
set_property PACKAGE_PIN H27 [get_ports rx1_rf_attn_le]
set_property PACKAGE_PIN K26 [get_ports rx1_if_attn_sin]
set_property PACKAGE_PIN L27 [get_ports rx1_if_attn_clk]
set_property PACKAGE_PIN M27 [get_ports rx1_if_attn_le]
set_property PACKAGE_PIN K27 [get_ports rx1_lna_en]
#set_property PACKAGE_PIN J24 [get_ports rx1_rf_attn_sin]
#set_property PACKAGE_PIN G27 [get_ports rx1_rf_attn_clk]
#set_property PACKAGE_PIN H27 [get_ports rx1_rf_attn_le]
#set_property PACKAGE_PIN K26 [get_ports rx1_if_attn_sin]
#set_property PACKAGE_PIN L27 [get_ports rx1_if_attn_clk]
#set_property PACKAGE_PIN M27 [get_ports rx1_if_attn_le]
#set_property PACKAGE_PIN K27 [get_ports rx1_lna_en]
# FMC1
set_property PACKAGE_PIN AE28 [get_ports tx0_rf_attn_sin]
set_property PACKAGE_PIN AB34 [get_ports tx0_rf_attn_clk]
set_property PACKAGE_PIN AA34 [get_ports tx0_rf_attn_le]
set_property PACKAGE_PIN AC34 [get_ports tx1_rf_attn_sin]
set_property PACKAGE_PIN AF34 [get_ports tx1_rf_attn_clk]
set_property PACKAGE_PIN AE33 [get_ports tx1_rf_attn_le]
set_property PACKAGE_PIN AD34 [get_ports txlo_drv_en]
set_property PACKAGE_PIN AF33 [get_ports rx0_rf_attn_sin]
set_property PACKAGE_PIN AG30 [get_ports rx0_rf_attn_clk]
set_property PACKAGE_PIN AF30 [get_ports rx0_rf_attn_le]
set_property PACKAGE_PIN U21 [get_ports rx0_if_attn_sin]
set_property PACKAGE_PIN AB20 [get_ports rx0_if_attn_clk]
set_property PACKAGE_PIN AA20 [get_ports rx0_if_attn_le]
set_property PACKAGE_PIN U22 [get_ports rx0_lna_en]
set_property PACKAGE_PIN AC28 [get_ports rx1_rf_attn_sin]
set_property PACKAGE_PIN AE30 [get_ports rx1_rf_attn_clk]
set_property PACKAGE_PIN AD29 [get_ports rx1_rf_attn_le]
set_property PACKAGE_PIN AC33 [get_ports rx1_if_attn_sin]
set_property PACKAGE_PIN AF32 [get_ports rx1_if_attn_clk]
set_property PACKAGE_PIN AE32 [get_ports rx1_if_attn_le]
set_property PACKAGE_PIN AD33 [get_ports rx1_lna_en]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_clk]
@@ -214,6 +250,8 @@ set_property PACKAGE_PIN D25 [get_ports jesd_sysref_n]
set_property IOSTANDARD LVDS [get_ports jesd_sysref_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports jesd_sysref_p]
set_property DQS_BIAS TRUE [get_ports jesd_sysref_p]
set_property DQS_BIAS TRUE [get_ports jesd_sysref_n]
set_property PACKAGE_PIN K5 [get_ports jesd_qpll0_refclk_n]
set_property PACKAGE_PIN K6 [get_ports jesd_qpll0_refclk_p]
@@ -222,13 +260,15 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
#set_property PACKAGE_PIN P5 [get_ports jesd_qpll0_refclk_n]
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}]
@@ -396,108 +436,21 @@ connect_debug_port u_ila_0/probe5 [get_nets [list util_reg_i/spi_shift_data]]
connect_debug_port u_ila_0/probe10 [get_nets [list util_reg_i/le_active]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list microblaze_bd_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1]]
connect_debug_port u_ila_0/clk [get_nets [list jesd_core_clk]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {util_reg_i/spi_bit_cnt_reg[0]} {util_reg_i/spi_bit_cnt_reg[1]} {util_reg_i/spi_bit_cnt_reg[2]} {util_reg_i/spi_bit_cnt_reg[3]} {util_reg_i/spi_bit_cnt_reg[4]} {util_reg_i/spi_bit_cnt_reg[5]} {util_reg_i/spi_bit_cnt_reg[6]} {util_reg_i/spi_bit_cnt_reg[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {util_reg_i/reg_spi_data[0]} {util_reg_i/reg_spi_data[1]} {util_reg_i/reg_spi_data[2]} {util_reg_i/reg_spi_data[3]} {util_reg_i/reg_spi_data[4]} {util_reg_i/reg_spi_data[5]} {util_reg_i/reg_spi_data[6]} {util_reg_i/reg_spi_data[7]} {util_reg_i/reg_spi_data[8]} {util_reg_i/reg_spi_data[9]} {util_reg_i/reg_spi_data[10]} {util_reg_i/reg_spi_data[11]} {util_reg_i/reg_spi_data[12]} {util_reg_i/reg_spi_data[13]} {util_reg_i/reg_spi_data[14]} {util_reg_i/reg_spi_data[15]} {util_reg_i/reg_spi_data[16]} {util_reg_i/reg_spi_data[17]} {util_reg_i/reg_spi_data[18]} {util_reg_i/reg_spi_data[19]} {util_reg_i/reg_spi_data[20]} {util_reg_i/reg_spi_data[21]} {util_reg_i/reg_spi_data[22]} {util_reg_i/reg_spi_data[23]} {util_reg_i/reg_spi_data[24]} {util_reg_i/reg_spi_data[25]} {util_reg_i/reg_spi_data[26]} {util_reg_i/reg_spi_data[27]} {util_reg_i/reg_spi_data[28]} {util_reg_i/reg_spi_data[29]} {util_reg_i/reg_spi_data[30]} {util_reg_i/reg_spi_data[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {util_reg_i/spi_clk_cnt_reg[0]} {util_reg_i/spi_clk_cnt_reg[1]} {util_reg_i/spi_clk_cnt_reg[2]} {util_reg_i/spi_clk_cnt_reg[3]} {util_reg_i/spi_clk_cnt_reg[4]} {util_reg_i/spi_clk_cnt_reg[5]} {util_reg_i/spi_clk_cnt_reg[6]} {util_reg_i/spi_clk_cnt_reg[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 5 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {util_reg_i/le_count_reg[0]} {util_reg_i/le_count_reg[1]} {util_reg_i/le_count_reg[2]} {util_reg_i/le_count_reg[3]} {util_reg_i/le_count_reg[4]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list util_reg_i/start_spi_transaction]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list tx0_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list tx0_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list tx0_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list rx0_if_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list rx0_if_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list rx0_if_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list rx0_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list rx0_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list rx0_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list rx1_if_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list rx1_if_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list rx1_if_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list rx1_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list rx1_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list rx1_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list tx1_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list tx1_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list tx1_rf_attn_sin_OBUF]]
set_property port_width 1 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list microblaze_bd_i/jesd/util_ds_buf_1_IBUF_OUT]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]

5381
radar_alinx_kintex.srcs/sources_1/bd/microblaze_bd/microblaze_bd.bd
View File

File diff suppressed because it is too large Load Diff

45
radar_alinx_kintex.srcs/sources_1/hdl/pulse_generator.v Executable file
View File

@@ -0,0 +1,45 @@
`resetall
`timescale 1ns / 1ps
`default_nettype none
module pulse_generator #
(
parameter integer COUNTER_BITS = 28
)
(
input wire clk,
input wire rst,
input wire [COUNTER_BITS-1:0] pulse_length,
output wire start_of_pulse,
output wire pulse_out
);
reg [COUNTER_BITS-1:0] pulse_cnt;
reg pulse_active;
assign pulse_out = pulse_active;
always @ (posedge clk) begin
if (rst == 1'b1) begin
pulse_cnt <= 0;
end else begin
if (start_of_pulse) begin
pulse_active <= 1;
end
if (pulse_active) begin
pulse_cnt <= pulse_cnt - 1;
if (pulse_cnt == 0) begin
pulse_active <= 0;
end
end
end
end
endmodule
`resetall

15
radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v
View File

@@ -83,8 +83,8 @@ reg [27:0] reg_pri;
reg [27:0] reg_num_pulses;
reg [27:0] reg_inter_cpi;
reg [31:0] reg_pps_sec_set;
reg [31:0] reg_pulse_width [NUM_TIMING_PULSES-1:0];
reg [31:0] reg_pulse_start [NUM_TIMING_PULSES-1:0];
reg [27:0] reg_pulse_width [NUM_TIMING_PULSES-1:0];
reg [28:0] reg_pulse_start [NUM_TIMING_PULSES-1:0];
reg [63:0] system_time;
reg [63:0] pps_frac_sec;
@@ -141,7 +141,7 @@ generate
for (gen_reg = 0; gen_reg < NUM_TIMING_PULSES; gen_reg = gen_reg + 1) begin
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_pulse_start[gen_reg] <= 0;
reg_pulse_start[gen_reg] <= 28'hFFFFFF;
end else if (wren && waddr[11:0] == ('h080 + gen_reg*8)) begin
reg_pulse_start[gen_reg] <= wdata;
end
@@ -396,14 +396,17 @@ end
// ------------------------------
// Pulse Generators
// ------------------------------
reg [NUM_TIMING_PULSES-1:0] pulse_start;
reg [NUM_TIMING_PULSES-1:0] pulse_start;
reg [NUM_TIMING_PULSES-1:0] timing_pulses_i;
genvar j;
generate
for (j = 0; j < NUM_TIMING_PULSES; j = j + 1) begin
assign timing_pulses[j] = timing_pulses_i | reg_pulse_start[j][28];
always @ (posedge clk) begin
if (pri_cnt == reg_pulse_start[j]) begin
if (pri_cnt == reg_pulse_start[j][27:0]) begin
pulse_start[j] <= 1;
end else begin
pulse_start[j] <= 0;
@@ -415,7 +418,7 @@ generate
.rst(rst),
.pulse_length(reg_pulse_width[j]),
.start_of_pulse(pulse_start[j]),
.pulse_out(timing_pulses[j])
.pulse_out(timing_pulses_i[j])
);
end

31
radar_alinx_kintex.srcs/sources_1/hdl/top.v
View File

@@ -42,6 +42,10 @@ module top #
output wire fmc_power_en,
input wire pps,
// I2C
inout wire i2c_scl,
inout wire i2c_sda,
// RF Control
output wire tx0_rf_attn_sin, //ADRF5730
output wire tx0_rf_attn_clk, //ADRF5730
@@ -286,6 +290,26 @@ module top #
.T(fmc_spi1_ss_t));
// I2C For changing regulator voltage
wire i2c_scl_i;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_i;
wire i2c_sda_o;
wire i2c_sda_t;
IOBUF i2c_scl_iobuf
(.I(i2c_scl_o),
.IO(i2c_scl),
.O(i2c_scl_i),
.T(i2c_scl_t));
IOBUF i2c_sda_iobuf
(.I(i2c_sda_o),
.IO(i2c_sda),
.O(i2c_sda_i),
.T(i2c_sda_t));
// ------------------------------
// BD
// ------------------------------
@@ -370,6 +394,13 @@ module top #
microblaze_bd microblaze_bd_i
(
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
.STARTUP_IO_cfgclk(),
.STARTUP_IO_cfgmclk(),
.STARTUP_IO_eos(),

4
radar_alinx_kintex.srcs/sources_1/ip/axis_switch_0/axis_switch_0.xci
View File

@@ -350,9 +350,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/clock_converter/clock_converter.xci
View File

@@ -42,9 +42,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/data_fifo/data_fifo.xci
View File

@@ -60,9 +60,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci
View File

@@ -42,9 +42,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci
View File

@@ -39,9 +39,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

32
radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci
View File

@@ -23,7 +23,7 @@
"INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"INS_LOSS_NYQ": [ { "value": "20", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -31,18 +31,18 @@
"PCIE_USERCLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_PLL_TYPE": [ { "value": "QPLL0", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ],
"RX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_PLL_TYPE": [ { "value": "QPLL0", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -50,7 +50,7 @@
"RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
"RX_JTOL_FC": [ { "value": "6.1862627", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ],
@@ -168,7 +168,7 @@
"LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ],
"ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PRESET": [ { "value": "GTH-10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
@@ -181,9 +181,9 @@
"SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"TXPROGDIV_FREQ_SOURCE": [ { "value": "QPLL0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -830,9 +830,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@@ -874,10 +874,10 @@
"gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gthrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gthrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll0refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll1clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll1refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll0clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll1clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll1refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxgearboxslip_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"txheader_in": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
"txsequence_in": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ],

20
radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci
View File

@@ -23,7 +23,7 @@
"INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"INS_LOSS_NYQ": [ { "value": "20", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -32,17 +32,17 @@
"TX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_PLL_TYPE": [ { "value": "QPLL0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ],
"RX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_PLL_TYPE": [ { "value": "QPLL0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -50,7 +50,7 @@
"RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
"RX_JTOL_FC": [ { "value": "6.1862627", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ],
@@ -168,7 +168,7 @@
"LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ],
"ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PRESET": [ { "value": "GTH-10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "14", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
@@ -181,9 +181,9 @@
"SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"TXPROGDIV_FREQ_SOURCE": [ { "value": "QPLL0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -830,9 +830,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/hdr_fifo/hdr_fifo.xci
View File

@@ -60,9 +60,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

20
radar_alinx_kintex.srcs/sources_1/ip/hdr_mem/hdr_mem.xci
View File

@@ -34,17 +34,17 @@
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Operating_Mode_A": [ { "value": "NO_CHANGE", "resolve_type": "user", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Operating_Mode_A": [ { "value": "NO_CHANGE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ],
"Write_Width_B": [ { "value": "64", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Read_Width_B": [ { "value": "64", "resolve_type": "user", "usage": "all" } ],
"Read_Width_B": [ { "value": "64", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_B": [ { "value": "Use_ENB_Pin", "resolve_type": "user", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -66,10 +66,10 @@
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -166,9 +166,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci
View File

@@ -60,9 +60,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

18
radar_alinx_kintex.srcs/sources_1/ip/wf_memory/wf_memory.xci
View File

@@ -14,7 +14,7 @@
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -34,17 +34,17 @@
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "resolve_type": "user", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ],
"Write_Width_B": [ { "value": "128", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Read_Width_B": [ { "value": "128", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
"Enable_B": [ { "value": "Use_ENB_Pin", "resolve_type": "user", "usage": "all" } ],
"Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -66,10 +66,10 @@
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Write_Rate": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -166,9 +166,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
radar_alinx_kintex.srcs/sources_1/ip/width_converter/width_converter.xci
View File

@@ -39,9 +39,9 @@
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "C" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

BIN
radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
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Binary file not shown.