bkiedinger/castelion_radar_alinx_kintex
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this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

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This commit is contained in:
bkiedinger@gmail.com
2025-04-25 06:26:07 -05:00
parent 729d034a13
commit 8a1a6ea770
30 changed files with 22794 additions and 22500 deletions
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187
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
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@@ -11,6 +11,7 @@ set_property CFGBVS VCCO [current_design]
#-------------------------------------------
set_false_path -from [get_cells util_reg_i/reg_*]
set_false_path -from [get_cells timing_engine_i/reg_*]
set_false_path -from [get_cells timing_engine_i/genblk1*reg_*]
set_false_path -from [get_cells timing_engine_i/system_time_start_of_cpi*]
set_false_path -from [get_cells *digital_rx_chain_i/reg_*]
set_false_path -from [get_cells waveform_gen_i/reg_*]
@@ -32,32 +33,67 @@ set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_200_n]
# set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_p]
# set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_n]
#-------------------------------------------
# I2C
#-------------------------------------------
set_property PACKAGE_PIN P24 [get_ports i2c_scl]
set_property PACKAGE_PIN P25 [get_ports i2c_sda]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda]
#-------------------------------------------
# RF Attenautors
#-------------------------------------------
set_property PACKAGE_PIN G25 [get_ports tx0_rf_attn_sin]
set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk]
set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le]
set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin]
set_property PACKAGE_PIN P23 [get_ports tx1_rf_attn_clk]
set_property PACKAGE_PIN R23 [get_ports tx1_rf_attn_le]
set_property PACKAGE_PIN K25 [get_ports txlo_drv_en]
# FMC2
#set_property PACKAGE_PIN G25 [get_ports tx0_rf_attn_sin]
#set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk]
#set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le]
#set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin]
#set_property PACKAGE_PIN P23 [get_ports tx1_rf_attn_clk]
#set_property PACKAGE_PIN R23 [get_ports tx1_rf_attn_le]
#set_property PACKAGE_PIN K25 [get_ports txlo_drv_en]
set_property PACKAGE_PIN R25 [get_ports rx0_rf_attn_sin]
set_property PACKAGE_PIN T25 [get_ports rx0_rf_attn_clk]
set_property PACKAGE_PIN T24 [get_ports rx0_rf_attn_le]
set_property PACKAGE_PIN AM11 [get_ports rx0_if_attn_sin]
set_property PACKAGE_PIN AF13 [get_ports rx0_if_attn_clk]
set_property PACKAGE_PIN AE13 [get_ports rx0_if_attn_le]
set_property PACKAGE_PIN AN11 [get_ports rx0_lna_en]
#set_property PACKAGE_PIN R25 [get_ports rx0_rf_attn_sin]
#set_property PACKAGE_PIN T25 [get_ports rx0_rf_attn_clk]
#set_property PACKAGE_PIN T24 [get_ports rx0_rf_attn_le]
#set_property PACKAGE_PIN AM11 [get_ports rx0_if_attn_sin]
#set_property PACKAGE_PIN AF13 [get_ports rx0_if_attn_clk]
#set_property PACKAGE_PIN AE13 [get_ports rx0_if_attn_le]
#set_property PACKAGE_PIN AN11 [get_ports rx0_lna_en]
set_property PACKAGE_PIN J24 [get_ports rx1_rf_attn_sin]
set_property PACKAGE_PIN G27 [get_ports rx1_rf_attn_clk]
set_property PACKAGE_PIN H27 [get_ports rx1_rf_attn_le]
set_property PACKAGE_PIN K26 [get_ports rx1_if_attn_sin]
set_property PACKAGE_PIN L27 [get_ports rx1_if_attn_clk]
set_property PACKAGE_PIN M27 [get_ports rx1_if_attn_le]
set_property PACKAGE_PIN K27 [get_ports rx1_lna_en]
#set_property PACKAGE_PIN J24 [get_ports rx1_rf_attn_sin]
#set_property PACKAGE_PIN G27 [get_ports rx1_rf_attn_clk]
#set_property PACKAGE_PIN H27 [get_ports rx1_rf_attn_le]
#set_property PACKAGE_PIN K26 [get_ports rx1_if_attn_sin]
#set_property PACKAGE_PIN L27 [get_ports rx1_if_attn_clk]
#set_property PACKAGE_PIN M27 [get_ports rx1_if_attn_le]
#set_property PACKAGE_PIN K27 [get_ports rx1_lna_en]
# FMC1
set_property PACKAGE_PIN AE28 [get_ports tx0_rf_attn_sin]
set_property PACKAGE_PIN AB34 [get_ports tx0_rf_attn_clk]
set_property PACKAGE_PIN AA34 [get_ports tx0_rf_attn_le]
set_property PACKAGE_PIN AC34 [get_ports tx1_rf_attn_sin]
set_property PACKAGE_PIN AF34 [get_ports tx1_rf_attn_clk]
set_property PACKAGE_PIN AE33 [get_ports tx1_rf_attn_le]
set_property PACKAGE_PIN AD34 [get_ports txlo_drv_en]
set_property PACKAGE_PIN AF33 [get_ports rx0_rf_attn_sin]
set_property PACKAGE_PIN AG30 [get_ports rx0_rf_attn_clk]
set_property PACKAGE_PIN AF30 [get_ports rx0_rf_attn_le]
set_property PACKAGE_PIN U21 [get_ports rx0_if_attn_sin]
set_property PACKAGE_PIN AB20 [get_ports rx0_if_attn_clk]
set_property PACKAGE_PIN AA20 [get_ports rx0_if_attn_le]
set_property PACKAGE_PIN U22 [get_ports rx0_lna_en]
set_property PACKAGE_PIN AC28 [get_ports rx1_rf_attn_sin]
set_property PACKAGE_PIN AE30 [get_ports rx1_rf_attn_clk]
set_property PACKAGE_PIN AD29 [get_ports rx1_rf_attn_le]
set_property PACKAGE_PIN AC33 [get_ports rx1_if_attn_sin]
set_property PACKAGE_PIN AF32 [get_ports rx1_if_attn_clk]
set_property PACKAGE_PIN AE32 [get_ports rx1_if_attn_le]
set_property PACKAGE_PIN AD33 [get_ports rx1_lna_en]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_clk]
@@ -214,6 +250,8 @@ set_property PACKAGE_PIN D25 [get_ports jesd_sysref_n]
set_property IOSTANDARD LVDS [get_ports jesd_sysref_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports jesd_sysref_p]
set_property DQS_BIAS TRUE [get_ports jesd_sysref_p]
set_property DQS_BIAS TRUE [get_ports jesd_sysref_n]
set_property PACKAGE_PIN K5 [get_ports jesd_qpll0_refclk_n]
set_property PACKAGE_PIN K6 [get_ports jesd_qpll0_refclk_p]
@@ -222,13 +260,15 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
#set_property PACKAGE_PIN P5 [get_ports jesd_qpll0_refclk_n]
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}]
@@ -396,108 +436,21 @@ connect_debug_port u_ila_0/probe5 [get_nets [list util_reg_i/spi_shift_data]]
connect_debug_port u_ila_0/probe10 [get_nets [list util_reg_i/le_active]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list microblaze_bd_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1]]
connect_debug_port u_ila_0/clk [get_nets [list jesd_core_clk]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {util_reg_i/spi_bit_cnt_reg[0]} {util_reg_i/spi_bit_cnt_reg[1]} {util_reg_i/spi_bit_cnt_reg[2]} {util_reg_i/spi_bit_cnt_reg[3]} {util_reg_i/spi_bit_cnt_reg[4]} {util_reg_i/spi_bit_cnt_reg[5]} {util_reg_i/spi_bit_cnt_reg[6]} {util_reg_i/spi_bit_cnt_reg[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {util_reg_i/reg_spi_data[0]} {util_reg_i/reg_spi_data[1]} {util_reg_i/reg_spi_data[2]} {util_reg_i/reg_spi_data[3]} {util_reg_i/reg_spi_data[4]} {util_reg_i/reg_spi_data[5]} {util_reg_i/reg_spi_data[6]} {util_reg_i/reg_spi_data[7]} {util_reg_i/reg_spi_data[8]} {util_reg_i/reg_spi_data[9]} {util_reg_i/reg_spi_data[10]} {util_reg_i/reg_spi_data[11]} {util_reg_i/reg_spi_data[12]} {util_reg_i/reg_spi_data[13]} {util_reg_i/reg_spi_data[14]} {util_reg_i/reg_spi_data[15]} {util_reg_i/reg_spi_data[16]} {util_reg_i/reg_spi_data[17]} {util_reg_i/reg_spi_data[18]} {util_reg_i/reg_spi_data[19]} {util_reg_i/reg_spi_data[20]} {util_reg_i/reg_spi_data[21]} {util_reg_i/reg_spi_data[22]} {util_reg_i/reg_spi_data[23]} {util_reg_i/reg_spi_data[24]} {util_reg_i/reg_spi_data[25]} {util_reg_i/reg_spi_data[26]} {util_reg_i/reg_spi_data[27]} {util_reg_i/reg_spi_data[28]} {util_reg_i/reg_spi_data[29]} {util_reg_i/reg_spi_data[30]} {util_reg_i/reg_spi_data[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {util_reg_i/spi_clk_cnt_reg[0]} {util_reg_i/spi_clk_cnt_reg[1]} {util_reg_i/spi_clk_cnt_reg[2]} {util_reg_i/spi_clk_cnt_reg[3]} {util_reg_i/spi_clk_cnt_reg[4]} {util_reg_i/spi_clk_cnt_reg[5]} {util_reg_i/spi_clk_cnt_reg[6]} {util_reg_i/spi_clk_cnt_reg[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 5 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {util_reg_i/le_count_reg[0]} {util_reg_i/le_count_reg[1]} {util_reg_i/le_count_reg[2]} {util_reg_i/le_count_reg[3]} {util_reg_i/le_count_reg[4]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list util_reg_i/start_spi_transaction]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list tx0_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list tx0_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list tx0_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list rx0_if_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list rx0_if_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list rx0_if_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list rx0_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list rx0_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list rx0_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list rx1_if_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list rx1_if_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list rx1_if_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list rx1_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list rx1_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list rx1_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list tx1_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list tx1_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list tx1_rf_attn_sin_OBUF]]
set_property port_width 1 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list microblaze_bd_i/jesd/util_ds_buf_1_IBUF_OUT]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]