bkiedinger/castelion_radar_alinx_kintex
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this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

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This commit is contained in:
bkiedinger@gmail.com
2025-04-25 06:26:07 -05:00
parent 729d034a13
commit 8a1a6ea770
30 changed files with 22794 additions and 22500 deletions
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45
radar_alinx_kintex.srcs/sources_1/hdl/pulse_generator.v Executable file
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@@ -0,0 +1,45 @@
`resetall
`timescale 1ns / 1ps
`default_nettype none
module pulse_generator #
(
parameter integer COUNTER_BITS = 28
)
(
input wire clk,
input wire rst,
input wire [COUNTER_BITS-1:0] pulse_length,
output wire start_of_pulse,
output wire pulse_out
);
reg [COUNTER_BITS-1:0] pulse_cnt;
reg pulse_active;
assign pulse_out = pulse_active;
always @ (posedge clk) begin
if (rst == 1'b1) begin
pulse_cnt <= 0;
end else begin
if (start_of_pulse) begin
pulse_active <= 1;
end
if (pulse_active) begin
pulse_cnt <= pulse_cnt - 1;
if (pulse_cnt == 0) begin
pulse_active <= 0;
end
end
end
end
endmodule
`resetall

15
radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v
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@@ -83,8 +83,8 @@ reg [27:0] reg_pri;
reg [27:0] reg_num_pulses;
reg [27:0] reg_inter_cpi;
reg [31:0] reg_pps_sec_set;
reg [31:0] reg_pulse_width [NUM_TIMING_PULSES-1:0];
reg [31:0] reg_pulse_start [NUM_TIMING_PULSES-1:0];
reg [27:0] reg_pulse_width [NUM_TIMING_PULSES-1:0];
reg [28:0] reg_pulse_start [NUM_TIMING_PULSES-1:0];
reg [63:0] system_time;
reg [63:0] pps_frac_sec;
@@ -141,7 +141,7 @@ generate
for (gen_reg = 0; gen_reg < NUM_TIMING_PULSES; gen_reg = gen_reg + 1) begin
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_pulse_start[gen_reg] <= 0;
reg_pulse_start[gen_reg] <= 28'hFFFFFF;
end else if (wren && waddr[11:0] == ('h080 + gen_reg*8)) begin
reg_pulse_start[gen_reg] <= wdata;
end
@@ -396,14 +396,17 @@ end
// ------------------------------
// Pulse Generators
// ------------------------------
reg [NUM_TIMING_PULSES-1:0] pulse_start;
reg [NUM_TIMING_PULSES-1:0] pulse_start;
reg [NUM_TIMING_PULSES-1:0] timing_pulses_i;
genvar j;
generate
for (j = 0; j < NUM_TIMING_PULSES; j = j + 1) begin
assign timing_pulses[j] = timing_pulses_i | reg_pulse_start[j][28];
always @ (posedge clk) begin
if (pri_cnt == reg_pulse_start[j]) begin
if (pri_cnt == reg_pulse_start[j][27:0]) begin
pulse_start[j] <= 1;
end else begin
pulse_start[j] <= 0;
@@ -415,7 +418,7 @@ generate
.rst(rst),
.pulse_length(reg_pulse_width[j]),
.start_of_pulse(pulse_start[j]),
.pulse_out(timing_pulses[j])
.pulse_out(timing_pulses_i[j])
);
end

31
radar_alinx_kintex.srcs/sources_1/hdl/top.v
View File

@@ -42,6 +42,10 @@ module top #
output wire fmc_power_en,
input wire pps,
// I2C
inout wire i2c_scl,
inout wire i2c_sda,
// RF Control
output wire tx0_rf_attn_sin, //ADRF5730
output wire tx0_rf_attn_clk, //ADRF5730
@@ -286,6 +290,26 @@ module top #
.T(fmc_spi1_ss_t));
// I2C For changing regulator voltage
wire i2c_scl_i;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_i;
wire i2c_sda_o;
wire i2c_sda_t;
IOBUF i2c_scl_iobuf
(.I(i2c_scl_o),
.IO(i2c_scl),
.O(i2c_scl_i),
.T(i2c_scl_t));
IOBUF i2c_sda_iobuf
(.I(i2c_sda_o),
.IO(i2c_sda),
.O(i2c_sda_i),
.T(i2c_sda_t));
// ------------------------------
// BD
// ------------------------------
@@ -370,6 +394,13 @@ module top #
microblaze_bd microblaze_bd_i
(
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
.STARTUP_IO_cfgclk(),
.STARTUP_IO_cfgmclk(),
.STARTUP_IO_eos(),