bkiedinger/castelion_radar_alinx_kintex
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this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

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bkiedinger@gmail.com
2025-04-25 06:26:07 -05:00
parent 729d034a13
commit 8a1a6ea770
30 changed files with 22794 additions and 22500 deletions
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radar_alinx_kintex.xpr
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@@ -7,7 +7,7 @@
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="c179ea77804d47eabf9d7773e858daa9"/>
<Option Name="Part" Val="xcku040-ffva1156-2-i"/>
<Option Name="Part" Val="xcku040-ffva1156-1-c"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
@@ -493,6 +493,30 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/clock_converter/clock_converter.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/data_fifo/data_fifo.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/width_converter/width_converter.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="top"/>
@@ -544,53 +568,8 @@
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="data_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/data_fifo" RelGenDir="$PGENDIR/data_fifo">
<File Path="$PSRCDIR/sources_1/ip/data_fifo/data_fifo.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="data_fifo"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="width_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/width_converter" RelGenDir="$PGENDIR/width_converter">
<File Path="$PSRCDIR/sources_1/ip/width_converter/width_converter.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="width_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="clock_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clock_converter" RelGenDir="$PGENDIR/clock_converter">
<File Path="$PSRCDIR/sources_1/ip/clock_converter/clock_converter.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="clock_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="wf_memory" Type="BlockSrcs" RelSrcDir="$PSRCDIR/wf_memory" RelGenDir="$PGENDIR/wf_memory">
<File Path="$PSRCDIR/sources_1/ip/wf_memory/wf_memory.xci">
<FileSet Name="microblaze_bd" Type="BlockSrcs" RelSrcDir="$PSRCDIR/microblaze_bd" RelGenDir="$PGENDIR/microblaze_bd">
<File Path="$PSRCDIR/sources_1/bd/microblaze_bd/microblaze_bd.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@@ -598,91 +577,7 @@
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="wf_memory"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="eth_xcvr_gt_full" Type="BlockSrcs" RelSrcDir="$PSRCDIR/eth_xcvr_gt_full" RelGenDir="$PGENDIR/eth_xcvr_gt_full">
<File Path="$PSRCDIR/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="eth_xcvr_gt_full"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="eth_xcvr_gt_channel" Type="BlockSrcs" RelSrcDir="$PSRCDIR/eth_xcvr_gt_channel" RelGenDir="$PGENDIR/eth_xcvr_gt_channel">
<File Path="$PSRCDIR/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="eth_xcvr_gt_channel"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pulse_buffer_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pulse_buffer_fifo" RelGenDir="$PGENDIR/pulse_buffer_fifo">
<File Path="$PSRCDIR/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="pulse_buffer_fifo"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="dig_rx_dwidth_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dig_rx_dwidth_converter" RelGenDir="$PGENDIR/dig_rx_dwidth_converter">
<File Path="$PSRCDIR/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="dig_rx_dwidth_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="dig_rx_clock_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dig_rx_clock_converter" RelGenDir="$PGENDIR/dig_rx_clock_converter">
<File Path="$PSRCDIR/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="dig_rx_clock_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="hdr_mem" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hdr_mem" RelGenDir="$PGENDIR/hdr_mem">
<File Path="$PSRCDIR/sources_1/ip/hdr_mem/hdr_mem.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="hdr_mem"/>
<Option Name="TopModule" Val="microblaze_bd"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
@@ -701,6 +596,104 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="hdr_mem" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hdr_mem" RelGenDir="$PGENDIR/hdr_mem">
<File Path="$PSRCDIR/sources_1/ip/hdr_mem/hdr_mem.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="hdr_mem"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="dig_rx_clock_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dig_rx_clock_converter" RelGenDir="$PGENDIR/dig_rx_clock_converter">
<File Path="$PSRCDIR/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="dig_rx_clock_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="dig_rx_dwidth_converter" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dig_rx_dwidth_converter" RelGenDir="$PGENDIR/dig_rx_dwidth_converter">
<File Path="$PSRCDIR/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="dig_rx_dwidth_converter"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pulse_buffer_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pulse_buffer_fifo" RelGenDir="$PGENDIR/pulse_buffer_fifo">
<File Path="$PSRCDIR/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="pulse_buffer_fifo"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="eth_xcvr_gt_channel" Type="BlockSrcs" RelSrcDir="$PSRCDIR/eth_xcvr_gt_channel" RelGenDir="$PGENDIR/eth_xcvr_gt_channel">
<File Path="$PSRCDIR/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="eth_xcvr_gt_channel"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="eth_xcvr_gt_full" Type="BlockSrcs" RelSrcDir="$PSRCDIR/eth_xcvr_gt_full" RelGenDir="$PGENDIR/eth_xcvr_gt_full">
<File Path="$PSRCDIR/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="eth_xcvr_gt_full"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="wf_memory" Type="BlockSrcs" RelSrcDir="$PSRCDIR/wf_memory" RelGenDir="$PGENDIR/wf_memory">
<File Path="$PSRCDIR/sources_1/ip/wf_memory/wf_memory.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="wf_memory"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="hdr_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hdr_fifo" RelGenDir="$PGENDIR/hdr_fifo">
<File Path="$PSRCDIR/sources_1/ip/hdr_fifo/hdr_fifo.xci">
<FileInfo>
@@ -715,20 +708,6 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="microblaze_bd" Type="BlockSrcs" RelSrcDir="$PSRCDIR/microblaze_bd" RelGenDir="$PGENDIR/microblaze_bd">
<File Path="$PSRCDIR/sources_1/bd/microblaze_bd/microblaze_bd.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="microblaze_bd"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@@ -752,7 +731,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="19">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-1-c" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -762,7 +741,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="data_fifo_synth_1" Type="Ft3:Synth" SrcSet="data_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="data_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/data_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/data_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/data_fifo_synth_1">
<Run Id="microblaze_bd_synth_1" Type="Ft3:Synth" SrcSet="microblaze_bd" Part="xcku040-ffva1156-1-c" ConstrsSet="microblaze_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/microblaze_bd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -772,7 +751,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="width_converter_synth_1" Type="Ft3:Synth" SrcSet="width_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="width_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/width_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/width_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/width_converter_synth_1">
<Run Id="axis_switch_0_synth_1" Type="Ft3:Synth" SrcSet="axis_switch_0" Part="xcku040-ffva1156-1-c" ConstrsSet="axis_switch_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axis_switch_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -782,7 +761,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clock_converter_synth_1" Type="Ft3:Synth" SrcSet="clock_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="clock_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clock_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clock_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/clock_converter_synth_1">
<Run Id="hdr_mem_synth_1" Type="Ft3:Synth" SrcSet="hdr_mem" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_mem" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_mem_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -792,7 +771,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="wf_memory_synth_1" Type="Ft3:Synth" SrcSet="wf_memory" Part="xcku040-ffva1156-2-i" ConstrsSet="wf_memory" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/wf_memory_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1">
<Run Id="dig_rx_clock_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_clock_converter" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_clock_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_clock_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -802,7 +781,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_full_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_full" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_full" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_full_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1">
<Run Id="dig_rx_dwidth_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_dwidth_converter" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_dwidth_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_dwidth_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -812,7 +791,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_channel_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_channel" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_channel" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_channel_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1">
<Run Id="pulse_buffer_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_fifo" Part="xcku040-ffva1156-1-c" ConstrsSet="pulse_buffer_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pulse_buffer_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -822,7 +801,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pulse_buffer_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pulse_buffer_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1">
<Run Id="eth_xcvr_gt_channel_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_channel" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_channel" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_channel_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -832,7 +811,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_dwidth_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_dwidth_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_dwidth_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_dwidth_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1">
<Run Id="eth_xcvr_gt_full_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_full" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_full" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_full_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -842,7 +821,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_clock_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_clock_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_clock_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_clock_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1">
<Run Id="wf_memory_synth_1" Type="Ft3:Synth" SrcSet="wf_memory" Part="xcku040-ffva1156-1-c" ConstrsSet="wf_memory" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/wf_memory_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -852,7 +831,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_mem_synth_1" Type="Ft3:Synth" SrcSet="hdr_mem" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_mem" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_mem_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1">
<Run Id="hdr_fifo_synth_1" Type="Ft3:Synth" SrcSet="hdr_fifo" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
@@ -862,37 +841,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axis_switch_0_synth_1" Type="Ft3:Synth" SrcSet="axis_switch_0" Part="xcku040-ffva1156-2-i" ConstrsSet="axis_switch_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axis_switch_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_fifo_synth_1" Type="Ft3:Synth" SrcSet="hdr_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="microblaze_bd_synth_1" Type="Ft3:Synth" SrcSet="microblaze_bd" Part="xcku040-ffva1156-2-i" ConstrsSet="microblaze_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/microblaze_bd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -910,7 +859,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="data_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="data_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="data_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/data_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/data_fifo_impl_1">
<Run Id="microblaze_bd_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="microblaze_bd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="microblaze_bd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -927,7 +876,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="width_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="width_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="width_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/width_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/width_converter_impl_1">
<Run Id="axis_switch_0_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="axis_switch_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axis_switch_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -944,7 +893,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clock_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="clock_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clock_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clock_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/clock_converter_impl_1">
<Run Id="hdr_mem_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="hdr_mem" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_mem_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -961,7 +910,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="wf_memory_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="wf_memory" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="wf_memory_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1">
<Run Id="dig_rx_clock_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_clock_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_clock_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -978,7 +927,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_full_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_full" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_full_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1">
<Run Id="dig_rx_dwidth_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="dig_rx_dwidth_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_dwidth_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -995,7 +944,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_channel_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_channel" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_channel_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1">
<Run Id="pulse_buffer_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="pulse_buffer_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pulse_buffer_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1012,7 +961,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pulse_buffer_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pulse_buffer_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_impl_1">
<Run Id="eth_xcvr_gt_channel_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_channel" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_channel_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1029,7 +978,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_dwidth_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_dwidth_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_dwidth_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_impl_1">
<Run Id="eth_xcvr_gt_full_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="eth_xcvr_gt_full" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="eth_xcvr_gt_full_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1046,7 +995,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_clock_converter_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_clock_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dig_rx_clock_converter_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_impl_1">
<Run Id="wf_memory_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-1-c" ConstrsSet="wf_memory" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="wf_memory_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
@@ -1063,58 +1012,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_mem_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_mem" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_mem_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axis_switch_0_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="axis_switch_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axis_switch_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hdr_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
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