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this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

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This commit is contained in:
bkiedinger@gmail.com
2025-04-25 06:26:07 -05:00
parent 729d034a13
commit 8a1a6ea770
30 changed files with 22794 additions and 22500 deletions
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4
vitis/radar/_ide/launch/IBERT.launch
View File

@@ -18,7 +18,7 @@
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uipl.powerup" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{&quot;microblaze_0&quot;:{&quot;xilinx.tcf.application&quot;:&quot;Debug/radar.elf&quot;,&quot;xilinx.tcf.datafiles&quot;:&quot;&quot;,&quot;xilinx.tcf.no_download&quot;:false,&quot;xilinx.tcf.profile_enabled&quot;:false,&quot;xilinx.tcf.profile_frequency&quot;:&quot;10000&quot;,&quot;xilinx.tcf.profile_non_int_frequency&quot;:&quot;150000000&quot;,&quot;xilinx.tcf.profile_non_int_high_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_low_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_use_count_instr&quot;:false,&quot;xilinx.tcf.profile_non_int_use_cumulate&quot;:false,&quot;xilinx.tcf.profile_non_intrusive_support&quot;:false,&quot;xilinx.tcf.profile_store_address&quot;:&quot;0x0&quot;,&quot;xilinx.tcf.profile_use_intrusive&quot;:false,&quot;xilinx.tcf.project&quot;:&quot;radar&quot;,&quot;xilinx.tcf.relocate&quot;:false,&quot;xilinx.tcf.relocate_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.reset&quot;:true,&quot;xilinx.tcf.stop_at_entry&quot;:false}}"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.selection" value="microblaze_0"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="true"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproject.name" value="radar"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uips.device" value="Auto Detect"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uips7.init" value="false"/>
@@ -26,7 +26,7 @@
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.apu" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.lock.step" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.rpu" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.system" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.system" value="true"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uitarget.peer" value="Local"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.active.build.config" value="Debug"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.application.type" value=""/>

5
vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_device.c
View File

@@ -17,7 +17,8 @@
#include "adi_ad9081_hal.h"
#define DEFAULT_DAC_FULLSCALE_CURRENT 26000 /*26mA*/
//#define DEFAULT_DAC_FULLSCALE_CURRENT 26000 /*26mA*/
#define DEFAULT_DAC_FULLSCALE_CURRENT 37000 /*37mA*/
/*============= C O D E ====================*/
int32_t adi_ad9081_device_boot_pre_clock(adi_ad9081_device_t *device)
{
@@ -1339,4 +1340,4 @@ int32_t adi_ad9081_device_startup_rx(adi_ad9081_device_t *device, uint8_t cddcs,
return API_CMS_ERROR_OK;
}
/*! @} */
/*! @} */

2
vitis/radar/src/ad9081_app_helper.c
View File

@@ -37,8 +37,6 @@ extern uint8_t rx_fddc_dcm[][8];
extern uint8_t rx_cddc_c2r[][4];
extern uint8_t rx_fddc_c2r[8];
extern uint8_t jtx_logiclane_mapping_pe_brd[2][8];
extern uint8_t jtx_logiclane_mapping_ce_brd[2][8];
extern adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2];
extern adi_cms_jesd_param_t jrx_param[];

42
vitis/radar/src/data_converter_setup.c
View File

@@ -32,9 +32,6 @@ extern uint8_t rx_fddc_dcm[][8];
extern uint8_t rx_cddc_c2r[][4];
extern uint8_t rx_fddc_c2r[8];
extern uint8_t jtx_logiclane_mapping_pe_brd[2][8];
extern uint8_t jtx_logiclane_mapping_ce_brd[2][8];
extern adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2];
extern adi_cms_jesd_param_t jrx_param[];
extern adi_cms_jesd_param_t jtx_param[][2];
@@ -73,7 +70,7 @@ void setup_data_converter() {
hmc7044_init();
// select use case
int uc = 0;
int uc = 1;
uint64_t app_jrx_lane_rate = 0;
uint64_t app_jtx_lane_rate[2] = {0};
@@ -153,7 +150,8 @@ void setup_data_converter() {
}
},
.clk_info = {
.sysref_mode = SYSREF_NONE,
// .sysref_mode = SYSREF_NONE,
.sysref_mode = SYSREF_CONT,
}
};
@@ -210,6 +208,7 @@ void setup_data_converter() {
hmc_out_ch &= ~(HMC7044_OP_CH_3 | HMC7044_OP_CH_13);
hmc_out_204c[3] = 0;
hmc_out_204c[13] = 0;
xil_printf("Disabling Sysref!!!!!!!\r\n");
}
if (err = adi_hmc7044_device_init(&hmc7044_dev), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
@@ -377,17 +376,17 @@ void setup_data_converter() {
printf("APP: Phase offset between incoming SYSREF and internal LMFC/LEMC: %d DAC clock units\n", phase);
// printf("APP: JESD RX Synchronization Mode: %s\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
// /* Power down Sysref Receiver circuitry*/
// if (err = adi_ad9081_jesd_sysref_input_mode_set(&ad9081_dev, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, COUPLING_AC), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// /* Perform oneshot sync */
// if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 0), err != API_CMS_ERROR_OK){
// if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
// printf("APP: JESD Oneshot Synchronization Not Completed");
// }
// error_print(__LINE__, err);
// }
printf("APP: JESD RX Synchronization Mode: %s\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
/* Power down Sysref Receiver circuitry*/
if (err = adi_ad9081_jesd_sysref_input_mode_set(&ad9081_dev, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, COUPLING_AC), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Perform oneshot sync */
if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 0), err != API_CMS_ERROR_OK){
if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
printf("APP: JESD Oneshot Synchronization Not Completed");
}
error_print(__LINE__, err);
}
/* SYSTEM Link Bring Up Sequenece
* Check AD9081 JESD PLL Lock Status
@@ -543,12 +542,23 @@ void setup_data_converter() {
vTaskDelay(100);
}
xil_printf("* Block sync achieved\r\n");
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
xil_printf("Wait for Extended Multiblock lock\r\n");
val = 0;
while ((val & STATUS_EMB_LOCK_BIT) != STATUS_EMB_LOCK_BIT) {
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
xil_printf("RX EMB: 0x%x\r\n", Xil_In32(JESD_RX + CTRL_MB_IN_EMB));
// for (int i = 0; i < 8; i++) {
// // Clear Error Counts
// uint32_t err_cnt = Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x10);
// xil_printf(" Lane %d STAT_RX_ERROR_CNT0 = 0x%x\r\n", err_cnt);
// }
vTaskDelay(100);
}
xil_printf("* Extended Multiblock lock achieved\r\n");

8
vitis/radar/src/hmc7044/src/adi_hmc7044_device.c
View File

@@ -502,7 +502,15 @@ int32_t adi_hmc7044_clk_config(adi_hmc7044_device_t *device, adi_hmc7044_clk_in_
/*Configure Clockout Frequencies*/
for (i = 0; i < HMC7044_NOF_OP_CH; i++) {
if (i == 10) {
xil_printf("Clk Out %d LVDS \r\n", i);
hmc_driver_config.mode = SIGNAL_LVDS;
} else if (i == 13) {
xil_printf("Clk Out %d LVDS \r\n", i);
hmc_driver_config.mode = SIGNAL_LVDS;
hmc_driver_config.mode = SIGNAL_LVDS;
} else if (i == 6) {
xil_printf("Clk Out %d LVDS \r\n", i);
hmc_driver_config.mode = SIGNAL_LVDS;
} else {
hmc_driver_config.mode = SIGNAL_CML;
}

3
vitis/radar/src/main.c
View File

@@ -115,6 +115,7 @@ void main_task( void *pvParameters ) {
while (1) {
toggleBit(0x40050008, 0); // Toggle LED
vTaskDelay(100);
}
}
@@ -133,7 +134,7 @@ int main(void) {
xTaskCreate( main_task,
( const char * ) "main",
0x10000,
0x20000,
NULL,
TASK_PRIORITY_MAIN,
NULL );

38
vitis/radar/src/uc_settings.c
View File

@@ -41,11 +41,9 @@ build a usecase parameters for a custom application.
*
*/
uint64_t clk_hz[][4] = {
/*dev_ref, fpga_ref, dac_clk, adc_clk */ /* UC, JESD, Crystal type, Lane rate, Comments */
// { 125e6, 275e6, 6000e6, 2000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
// { 125e6, 275e6, 8000e6, 4000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
// { 118.75e6, 237.5e6, 11400e6, 3800e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
{ 93.75e6, 187.5e6, 9000e6, 3000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
/*dev_ref, fpga_ref, dac_clk, adc_clk */
{ 93.75e6, 187.5e6, 9000e6, 3000e6 },
{ 118.75e6, 237.5e6, 11400e6, 3800e6 },
}; // 204B
#if !defined(AD9207_ID) && !defined(AD9209_ID)
@@ -102,24 +100,27 @@ uint64_t clk_hz[][4] = {
//#define if_freq 10e6
uint8_t tx_dac_chan_xbar[][4] = { /* dac0, dac1, dac2, dac3 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc13*/
// { AD9081_DAC_CH_0, AD9081_DAC_CH_1 }, /* uc13*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 },
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 },
};
int64_t tx_main_shift[][4] = { /* dac0, dac1, dac2, dac3 */
{ tx_if_freq, tx_if_freq, tx_if_freq, tx_if_freq }, /* uc13*/
{ tx_if_freq, tx_if_freq, tx_if_freq, tx_if_freq }, /* uc13*/
};
int64_t tx_chan_shift[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
int8_t tx_chan_gain[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
uint8_t tx_interp[][2] = {
/* {main DUC Interpolation, Channelizer DUC Interpolation} */
{ 12, 1 }, /* uc13*/
// { 8, 1 }, /* uc13*/
{ 12, 1 }, /* uc13*/
};
#endif
@@ -132,7 +133,7 @@ uint8_t tx_interp[][2] = {
*/
uint8_t rx_cddc_select[] = {
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
// AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1, /* uc13*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
};
/* RX Main Path DDC NCO Frequency Configuration
@@ -146,6 +147,7 @@ uint8_t rx_cddc_select[] = {
int64_t rx_cddc_shift[][4] = {
/* {cddc0, cddc1, cddc2, cddc3 }*/
{ rx_if_freq, rx_if_freq, rx_if_freq, rx_if_freq}, /* uc13*/
{ rx_if_freq, rx_if_freq, rx_if_freq, rx_if_freq}, /* uc13*/
};
/* RX Main Path DDC Data Decimation
* List the ADC_Coarse DDCs desired data decimation
@@ -159,7 +161,7 @@ int64_t rx_cddc_shift[][4] = {
uint8_t rx_cddc_dcm[][4] = {
/*{cddc0, cddc1, cddc2, cddc3} */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
// { AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
};
/* RX Main Path DDC Has Optional Complex to Real Convertor
* rx_cddc_c2r sets the enable for Complex to Real Converter per Main/Coarse DDC
@@ -173,6 +175,7 @@ uint8_t rx_cddc_dcm[][4] = {
*/
uint8_t rx_cddc_c2r[][4] = { /* cddc0, cddc1, cddc2, cddc3 */
{ 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0 }, /* uc13*/
};
/* RX Channelizer/Fine DDC Datapath Selection
* List the ADC Fine DDCs data path for routing Data from Main/ Coarse DDC Datapth to the JESD Tx
@@ -189,7 +192,7 @@ uint8_t rx_cddc_c2r[][4] = { /* cddc0, cddc1, cddc2, cddc3 */
*/
uint8_t rx_fddc_select[] = {
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
// AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc13*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
};
/* RX Channelizer Path DDC NCO Frequency Configuration
* List the ADC_Fine DDCs desired Frequency Shift
@@ -202,6 +205,7 @@ uint8_t rx_fddc_select[] = {
int64_t rx_fddc_shift[][8] = {
/* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
/* RX Channelizer Data Decimation
* List the ADC Fine DDCs desired data decimation
@@ -215,7 +219,7 @@ int64_t rx_fddc_shift[][8] = {
*/
uint8_t rx_fddc_dcm[][8] = { /* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
// { AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
};
uint8_t rx_fddc_c2r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* uc */
@@ -238,7 +242,7 @@ uint8_t rx_fddc_c2r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* uc */
*/
adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2] = {
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
// { { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc13.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
};
/* Total Decimation Settings */
@@ -255,19 +259,17 @@ adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2] = {
*/
uint8_t jtx_chip_dcm[][2] = {
{ 4 }, /* uc13.link0 */
// { 4 }, /* uc13.link0 */
{ 4 }, /* uc13.link0 */
};
uint8_t jtx_logiclane_mapping_pe_brd[2][8] = { { 0, 1, 2, 3, 4, 5, 6, 7 }, { 4, 5, 6, 7, 0, 1, 2, 3 } };
uint8_t jtx_logiclane_mapping_ce_brd[2][8] = { { 6, 4, 3, 2, 1, 0, 7, 5 }, { 2, 0, 7, 7, 7, 7, 3, 1 } };
adi_cms_jesd_param_t jrx_param[] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 15 }, /* uc13: txmode = 378 */
// { 8, 1, 4, 1, 0, 256, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 17 }, /* uc13: txmode = 378 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 15 }, /* uc13: txmode = 378 */
};
adi_cms_jesd_param_t jtx_param[][2] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode C2R ModeS */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16, 0, 0 } }, /* uc13: rxmode = 227, link0 */
// { { 8, 1, 4, 1, 0, 256, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 18, 0, 0 } }, /* uc13: rxmode = 227, link0 */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16, 0, 0 } }, /* uc13: rxmode = 227, link0 */
};

38879
vitis/radar_system/_ide/flash/radar.elf.srec
View File

File diff suppressed because it is too large Load Diff

5
vitis/radar_system/_ide/scripts/ibert.tcl
View File

@@ -10,11 +10,14 @@
# source /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar_system/_ide/scripts/ibert.tcl
#
connect -url tcp:127.0.0.1:3121
targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && level==0 && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-13822093-0"}
fpga -file /home/bkiedinger/projects/castelion/radar_alinx_kintex_ibert/radar_alinx_kintex.runs/impl_1/top.bit
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
loadhw -hw /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/hw/top.xsa -regs
configparams mdm-detect-bscan-mask 2
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
rst -processor
rst -system
after 3000
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
dow /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar/Debug/radar.elf
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }