bkiedinger/castelion_radar_alinx_kintex
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this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

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bkiedinger@gmail.com
2025-04-25 06:26:07 -05:00
parent 729d034a13
commit 8a1a6ea770
30 changed files with 22794 additions and 22500 deletions
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42
vitis/radar/src/data_converter_setup.c
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@@ -32,9 +32,6 @@ extern uint8_t rx_fddc_dcm[][8];
extern uint8_t rx_cddc_c2r[][4];
extern uint8_t rx_fddc_c2r[8];
extern uint8_t jtx_logiclane_mapping_pe_brd[2][8];
extern uint8_t jtx_logiclane_mapping_ce_brd[2][8];
extern adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2];
extern adi_cms_jesd_param_t jrx_param[];
extern adi_cms_jesd_param_t jtx_param[][2];
@@ -73,7 +70,7 @@ void setup_data_converter() {
hmc7044_init();
// select use case
int uc = 0;
int uc = 1;
uint64_t app_jrx_lane_rate = 0;
uint64_t app_jtx_lane_rate[2] = {0};
@@ -153,7 +150,8 @@ void setup_data_converter() {
}
},
.clk_info = {
.sysref_mode = SYSREF_NONE,
// .sysref_mode = SYSREF_NONE,
.sysref_mode = SYSREF_CONT,
}
};
@@ -210,6 +208,7 @@ void setup_data_converter() {
hmc_out_ch &= ~(HMC7044_OP_CH_3 | HMC7044_OP_CH_13);
hmc_out_204c[3] = 0;
hmc_out_204c[13] = 0;
xil_printf("Disabling Sysref!!!!!!!\r\n");
}
if (err = adi_hmc7044_device_init(&hmc7044_dev), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
@@ -377,17 +376,17 @@ void setup_data_converter() {
printf("APP: Phase offset between incoming SYSREF and internal LMFC/LEMC: %d DAC clock units\n", phase);
// printf("APP: JESD RX Synchronization Mode: %s\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
// /* Power down Sysref Receiver circuitry*/
// if (err = adi_ad9081_jesd_sysref_input_mode_set(&ad9081_dev, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, COUPLING_AC), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// /* Perform oneshot sync */
// if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 0), err != API_CMS_ERROR_OK){
// if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
// printf("APP: JESD Oneshot Synchronization Not Completed");
// }
// error_print(__LINE__, err);
// }
printf("APP: JESD RX Synchronization Mode: %s\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
/* Power down Sysref Receiver circuitry*/
if (err = adi_ad9081_jesd_sysref_input_mode_set(&ad9081_dev, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, COUPLING_AC), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Perform oneshot sync */
if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 0), err != API_CMS_ERROR_OK){
if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
printf("APP: JESD Oneshot Synchronization Not Completed");
}
error_print(__LINE__, err);
}
/* SYSTEM Link Bring Up Sequenece
* Check AD9081 JESD PLL Lock Status
@@ -543,12 +542,23 @@ void setup_data_converter() {
vTaskDelay(100);
}
xil_printf("* Block sync achieved\r\n");
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
xil_printf("Wait for Extended Multiblock lock\r\n");
val = 0;
while ((val & STATUS_EMB_LOCK_BIT) != STATUS_EMB_LOCK_BIT) {
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
xil_printf("RX EMB: 0x%x\r\n", Xil_In32(JESD_RX + CTRL_MB_IN_EMB));
// for (int i = 0; i < 8; i++) {
// // Clear Error Counts
// uint32_t err_cnt = Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x10);
// xil_printf(" Lane %d STAT_RX_ERROR_CNT0 = 0x%x\r\n", err_cnt);
// }
vTaskDelay(100);
}
xil_printf("* Extended Multiblock lock achieved\r\n");