remove file

cpp/bandwidth_test_readme.md

@@ -0,0 +1,12 @@
+sudo fio --name=seq_write_test --filename=/media/hptnvme/fio.test --rw=write --bs=4M --ioengine=libaio --direct=1 --size=100G --numjobs=1 --runtime=100 --time_based --group_reporting --log_avg_msec=1000 --write_bw_log=/media/hptnvme/seq_write_bw
+
+gnuplot -e "
+    set datafile separator ',';
+    set term png size 1200,600 enhanced font 'Arial,10';
+    set output 'fio_bandwidth_chart.png';
+    set title 'Sustained Sequential Write Bandwidth Over Time';
+    set xlabel 'Time (Seconds)';
+    set ylabel 'Bandwidth (MiB/s)';
+    set grid;
+    plot '/media/hptnvme/seq_write_bw_bw.1.log' using (\$1/1000):(\$2/1024) with lines title 'Write Speed' linecolor rgb '#0072B2' lw 2;
+"

cpp/data_recorder.cpp

@@ -59,15 +59,15 @@ DataRecorder::DataRecorder() {
     allocate_memory();
 
     // Prep access to PL registers
-    plfd = open("/dev/wsrpl0", O_RDWR);
+    plfd = open("/dev/drexpl0", O_RDWR);
     if (plfd < 0){
-        printf("Failed to open %s\n", "/dev/wsrpl0");
+        printf("Failed to open %s\n", "/dev/drexpl0");
     }
 
     plmmap = (uint32_t *)mmap(NULL, 0x1000000, PROT_WRITE | PROT_READ, MAP_SHARED, plfd, 0);
 
     if (plmmap < (uint32_t *)0){
-        printf("Failed to mmap %s\n", "/dev/wsrpl0");
+        printf("Failed to mmap %s\n", "/dev/drexpl0");
         close(plfd);
     }
 
@@ -196,8 +196,7 @@ void DataRecorder::write_data(int ch_ind) {
 
     int ret;
 
-    int write_chunk_size = BUFFER_SIZE;
-
+    int write_chunk_size = 4 * 1024 * 1024;
     int bytes_avail = 0;
     int write_ind = 0;
     int sem_value;
@@ -218,41 +217,43 @@ void DataRecorder::write_data(int ch_ind) {
             continue;
         }
 
-        if (num_bytes_to_write[ch_ind][buffer_ind] != BUFFER_SIZE) {
-            printf("hmmmmmmmmm %d", num_bytes_to_write[ch_ind][buffer_ind]);
+        bytes_avail += num_bytes_to_write[ch_ind][buffer_ind];
+        buffer_ind++;
+        buffer_ind = buffer_ind % NUM_BUFFERS;   
+        
+        // Detect buffer warp condition and write data
+        bool wrap = false;
+        if ((write_ind + bytes_avail) > (OVERALL_BUFFER_SIZE - BUFFER_SIZE)) {
+            // printf("write bla %d, %d\n", write_ind, bytes_avail);
+            wrap = true;
         }
 
-        bytes_avail += num_bytes_to_write[ch_ind][buffer_ind];
-
-        if (bytes_avail >= write_chunk_size) {
-            sem_getvalue(&buffer_ready_sem[ch_ind], &sem_value);
+        if ((bytes_avail >= write_chunk_size) || wrap) {
             int cnt = write(out_fd[ch_ind], &(data_buffer[ch_ind][write_ind]), bytes_avail);
             if (cnt < 0)
             {
-                printf("File write error!\n");
+                printf("File write error! %d, %d, %d\n", cnt, write_ind, bytes_avail);
+                return;
             }
             total_bytes[ch_ind] += cnt;
             write_ind += bytes_avail;
             bytes_avail = 0;
-            write_ind = write_ind % OVERALL_BUFFER_SIZE;
+
+            if (wrap) {
+                write_ind = 0;
+            }
         }
+    }
 
-        buffer_ind++;
-        buffer_ind = buffer_ind % NUM_BUFFERS;
-
-        // int cnt = write(out_fd[ch_ind], &(data_buffer[ch_ind][buffer_ind*BUFFER_SIZE]), num_bytes_to_write[ch_ind][buffer_ind]);
-        // if (cnt < 0)
-        // {
-        //     printf("File write error! %d, %d, %d, %p\n", ch_ind, buffer_ind, errno, &(data_buffer[ch_ind][buffer_ind*BUFFER_SIZE]));
-        // }
-        // total_bytes[ch_ind] += cnt;
-        // buffer_ind++;
-        // buffer_ind = buffer_ind % NUM_USERSPACE_BUFFERS;
+    if (bytes_avail > 0) {
+        int cnt = write(out_fd[ch_ind], &(data_buffer[ch_ind][write_ind]), bytes_avail);
+        total_bytes[ch_ind] += cnt;
+        printf("Writing last chunk, Total Recorded (MB) %0.2f\n", total_bytes[ch_ind] / 1e6);
     }
 
     sem_getvalue(&buffer_ready_sem[ch_ind], &sem_value);
 
-    printf("Exiting Write Data Thread %d, %d\n", ch_ind, sem_value);
+    // printf("Exiting Write Data Thread %d, %d\n", ch_ind, sem_value);
 }
 
 void DataRecorder::set_validate_cnt_data(bool enable, uint32_t pri, uint32_t inter, uint32_t count) {
@@ -265,7 +266,7 @@ void DataRecorder::set_validate_cnt_data(bool enable, uint32_t pri, uint32_t int
 void DataRecorder::get_data(int ch_ind, int save_to_disk) {
 
     char* file;
-    asprintf(&file, "/dev/wsrdma%d", ch_ind);
+    asprintf(&file, "/dev/drexdma%d", ch_ind);
 
     // Start write to disk thread
     if (save_to_disk) {
@@ -278,27 +279,27 @@ void DataRecorder::get_data(int ch_ind, int save_to_disk) {
         return;
     }
 
-    wsrpcie_ioctl_t wsrpcie_ioctl;
+    drexpcie_ioctl_t drexpcie_ioctl;
 
-    wsrpcie_ioctl.cmd = WSRDMA_SET_NUM_BYTES;
-    wsrpcie_ioctl.offset = 0;
-    wsrpcie_ioctl.value = BUFFER_SIZE;
-    ioctl(fd, 0, &wsrpcie_ioctl);
+    drexpcie_ioctl.cmd = DREXDMA_SET_NUM_BYTES;
+    drexpcie_ioctl.offset = 0;
+    drexpcie_ioctl.value = BUFFER_SIZE;
+    ioctl(fd, 0, &drexpcie_ioctl);
 
-    wsrpcie_ioctl.cmd = WSRDMA_SET_NUM_BUFS;
-    wsrpcie_ioctl.offset = 0;
-    wsrpcie_ioctl.value = NUM_BUFFERS;
-    ioctl(fd, 0, &wsrpcie_ioctl);
+    drexpcie_ioctl.cmd = DREXDMA_SET_NUM_BUFS;
+    drexpcie_ioctl.offset = 0;
+    drexpcie_ioctl.value = NUM_BUFFERS;
+    ioctl(fd, 0, &drexpcie_ioctl);
 
-    wsrpcie_ioctl.cmd = WSRDMA_DMA_INIT;
-    wsrpcie_ioctl.offset = 0;
-    wsrpcie_ioctl.value = 0;
-    ioctl(fd, 0, &wsrpcie_ioctl);
+    drexpcie_ioctl.cmd = DREXDMA_DMA_INIT;
+    drexpcie_ioctl.offset = 0;
+    drexpcie_ioctl.value = 0;
+    ioctl(fd, 0, &drexpcie_ioctl);
 
-    wsrpcie_ioctl.cmd = WSRDMA_DMA_START;
-    wsrpcie_ioctl.offset = 0;
-    wsrpcie_ioctl.value = 0;
-    ioctl(fd, 0, &wsrpcie_ioctl);    
+    drexpcie_ioctl.cmd = DREXDMA_DMA_START;
+    drexpcie_ioctl.offset = 0;
+    drexpcie_ioctl.value = 0;
+    ioctl(fd, 0, &drexpcie_ioctl);    
 
 
     struct timespec ts_now;
@@ -307,6 +308,7 @@ void DataRecorder::get_data(int ch_ind, int save_to_disk) {
 
     total_bytes[ch_ind] = 0;
     long int bytes_since_last_update = 0;
+    long int total_bytes_received = 0;
     
     // For timing info
     clock_gettime(CLOCK_MONOTONIC, &ts_begin);
@@ -316,32 +318,34 @@ void DataRecorder::get_data(int ch_ind, int save_to_disk) {
     double print_period = 1;
 
     printf("Waiting for data\n");
-    uint32_t buffer_ind = 0;
+    uint32_t buffer_offset = 0;
+    uint32_t sem_ind = 0;
     uint32_t write_cnt = 0;
     bool init_cnt = true;
     uint64_t current_cnt;
     uint64_t pulse_cnt = 0;
 
     while (!exit_thread.load()) {   
-        int read_count = read(fd, &(data_buffer[ch_ind][buffer_ind*BUFFER_SIZE]), BUFFER_SIZE);
-        // reference to current data buffer
-        char * data_buf = &(data_buffer[ch_ind][buffer_ind*BUFFER_SIZE]);
+        int read_count = read(fd, &(data_buffer[ch_ind][buffer_offset]), BUFFER_SIZE);
         bytes_since_last_update += read_count;
+        total_bytes_received += read_count;
         clock_gettime(CLOCK_MONOTONIC, &ts_now);
 
         if (read_count) {
             // printf("read count %d\n", read_count);
 
             if (save_to_disk) {
-                num_bytes_to_write[ch_ind][buffer_ind] = read_count;
+                num_bytes_to_write[ch_ind][sem_ind] = read_count;
                 if (sem_post(&buffer_ready_sem[ch_ind]) == -1) {
                     printf("sem_post error\n");
                 }
+                sem_ind++;
+                sem_ind = sem_ind % NUM_BUFFERS;
             }
 
             if (validate_cnt_data) {
 
-                uint64_t * data = (uint64_t *)&(data_buffer[ch_ind][buffer_ind*BUFFER_SIZE]);
+                uint64_t * data = (uint64_t *)&(data_buffer[ch_ind][buffer_offset]);
                 int num_samp = read_count / (sizeof(uint64_t) * 2);
                 if (init_cnt) {
                     current_cnt = data[0];
@@ -366,8 +370,11 @@ void DataRecorder::get_data(int ch_ind, int save_to_disk) {
                 }
             }
 
-            buffer_ind++;
-            buffer_ind = buffer_ind % NUM_BUFFERS;
+            buffer_offset += read_count;
+            if (buffer_offset > (OVERALL_BUFFER_SIZE - BUFFER_SIZE)) {
+                // printf("reset recv buffer - %d\n", buffer_offset);
+                buffer_offset = 0;
+            }
         } else {
             // Small sleep if no data is available, without this each thread will peg a CPU core
             usleep(1);
@@ -380,32 +387,29 @@ void DataRecorder::get_data(int ch_ind, int save_to_disk) {
             double rate_last = (double)bytes_since_last_update / elapsed;
             clock_gettime(CLOCK_MONOTONIC, &ts_last_print);
             bytes_since_last_update = 0;
-            printf("Ch %d, Data Rate (MB/s) %0.2f, Data Rate last update (MB/s) %0.2f, Total Recorded (MB) %0.2f\n", ch_ind, rate/1e6, rate_last/1e6, total_bytes[ch_ind]/1e6);
+            printf("Ch %d, Data Rate (MB/s) %0.2f, Data Rate last update (MB/s) %0.2f, Total Recorded (MB) %0.2f, Total Received (MB) %0.2f\n", ch_ind, rate/1e6, rate_last/1e6, total_bytes[ch_ind]/1e6, total_bytes_received/1e6);
 
             recording_rate[ch_ind] = rate;          
         }
 
     }
 
-    wsrpcie_ioctl.cmd = WSRDMA_DMA_STOP;
-    wsrpcie_ioctl.offset = 0;
-    wsrpcie_ioctl.value = 0;
+    drexpcie_ioctl.cmd = DREXDMA_DMA_STOP;
+    drexpcie_ioctl.offset = 0;
+    drexpcie_ioctl.value = 0;
 
-    ioctl(fd, 0, &wsrpcie_ioctl);
+    ioctl(fd, 0, &drexpcie_ioctl);
 
-    wsrpcie_ioctl.cmd = WSRDMA_DMA_CLEAR;
-    wsrpcie_ioctl.offset = 0;
-    wsrpcie_ioctl.value = 0;
+    drexpcie_ioctl.cmd = DREXDMA_DMA_CLEAR;
+    drexpcie_ioctl.offset = 0;
+    drexpcie_ioctl.value = 0;
 
-    ioctl(fd, 0, &wsrpcie_ioctl);
+    ioctl(fd, 0, &drexpcie_ioctl);
 
     // Make sure write thread is done before closing file handle
     if (writer[ch_ind].joinable()) {
         writer[ch_ind].join();
     }           
-    
-    // Want to write out that last little bit of data if we didn't make it to a full chunk
-    
 
     close(fd);
     close(out_fd[ch_ind]);

cpp/data_recorder.h

@@ -8,27 +8,31 @@
 #include <string>
 #include <queue>
 
-#define UTIL_REG_BASE 0x100000
-#define TIMING_REG_BASE 0x110000
-#define DATA_GEN_REG_BASE 0x120000
+// #define UTIL_REG_BASE 0x100000
+// #define TIMING_REG_BASE 0x110000
+// #define DATA_GEN_REG_BASE 0x120000
 
-#define WSRDMA_DMA_INIT             0
-#define WSRDMA_DMA_CLEAR            1
-#define WSRDMA_DMA_START            2
-#define WSRDMA_DMA_STOP             3
-#define WSRDMA_SET_NUM_BUFS         4
-#define WSRDMA_SET_NUM_BYTES        5
-#define WSRDMA_GET_NUM_BUFS         6
-#define WSRDMA_GET_NUM_BYTES        7
-#define WSRDMA_GET_FREE_BUFS        8
+#define UTIL_REG_BASE 0x10000
+#define TIMING_REG_BASE 0x20000
+#define DATA_GEN_REG_BASE 0x30000
+
+#define DREXDMA_DMA_INIT             0
+#define DREXDMA_DMA_CLEAR            1
+#define DREXDMA_DMA_START            2
+#define DREXDMA_DMA_STOP             3
+#define DREXDMA_SET_NUM_BUFS         4
+#define DREXDMA_SET_NUM_BYTES        5
+#define DREXDMA_GET_NUM_BUFS         6
+#define DREXDMA_GET_NUM_BYTES        7
+#define DREXDMA_GET_FREE_BUFS        8
 
 typedef struct {
    unsigned int cmd;
    unsigned int offset;
    unsigned int value;
-} wsrpcie_ioctl_t;
+} drexpcie_ioctl_t;
 
-#define NUM_DMA_CH      2
+#define NUM_DMA_CH      4
 #define BUFFER_SIZE     (4 * 1024 * 1024)
 // #define BUFFER_SIZE     (8192)
 #define NUM_BUFFERS     128

cpp/test_data_recorder.cpp

@@ -1,16 +1,6 @@
-// sudo setpci -s 0000:05:00.0 0x78.w=293f
-/*
-https://forums.developer.nvidia.com/t/the-devctl-maxpayload-is-lower-than-devcap/319292
-Some example for how to use setpci.
-
-sudo setpci -s 0005:00:00.0 74.w (device capabilities register for x4)
-sudo setpci -s 0005:00:00.0 78.w ( Device Control register for x4) and write value for bits 7:5 as (001b) for 256 Bytes MPS
-
-You have to change 0005:00:00.0 to the device you are using here.
-
-*/
-
 #include "data_recorder.h"
+#include <unistd.h>
+
 int main() {
     // Instantiate the class
     DataRecorder dr;
@@ -20,19 +10,25 @@ int main() {
     // Setup Timing Engine and data generator to test
     uint32_t n_pulses = 128;
     float inter_cpi = 100e-6;
-    float pri = 84e-6;
-    uint32_t n_samples = 8192;
-    // float pri = 40e-6;
-    // uint32_t n_samples = 4096;
+    // float pri = 75e-6;
+    float pri = 100e-6;
+    uint32_t n_samples = 16384;
+    int test_time_ms = 10000;
+
+    // Set false to just pull data across the pcie and run the data validator.
+    // Set true to save data to disk
+    bool save_to_disk = false;
 
     float cpi_time = n_pulses * pri + inter_cpi;
     float cpi_num_bytes = n_pulses * n_samples * 16;
 
     float expected_data_rate = cpi_num_bytes / cpi_time / 1e6;
-    // PCIe Gen3 x4 Therotecial Max is 4GBPS, 
-    // 128B/120B encoding drops that to 3938 MBPS
-    // Assuming an MSP of 128 bytes (86.5% effeciency), that further drops to 3406 MBPS
-    // Currently achieving 3092 MBPS without errors which is ~90% of 3406 MBPS
+    // PCIe Gen3 x16 Theoretical Max is 16GBPS, 
+    // 128B/130B encoding drops that to 15753.8 MBPS
+    // Assuming an MSP of 128 bytes (84.2% effeciency), that further drops to 13264 MBPS
+    // Assuming an MSP of 256 bytes (91.4% effeciency), that further drops to 14399 MBPS
+    // Assuming an MSP of 512 bytes (95.5% effeciency), that further drops to 15044 MBPS  <- Threadripper box uses 512
+    // Currently achieving 13836 MBPS without errors which is ~92% of 15044 MBPS
     printf("Expected Data Rate - %.2f MBps Per Channel, Total %.2f\n", expected_data_rate, expected_data_rate * NUM_DMA_CH);
 
     dr.write_reg(TIMING_REG_BASE + 0x0, 1);
@@ -49,16 +45,18 @@ int main() {
     dr.set_validate_cnt_data(true, dr.read_reg(TIMING_REG_BASE + 0x4) + 1, dr.read_reg(TIMING_REG_BASE + 0x10) + 1, n_pulses);
 
     // Start listening for data
-    dr.start_recording("test.bin", 0);
+    dr.start_recording("/media/hptnvme/test.bin", save_to_disk);
+    sleep(1);
     // Start the timing engine so data starts flowing
     dr.write_reg(TIMING_REG_BASE + 0x0, 0);
     // Wait a while
-    std::this_thread::sleep_for(std::chrono::milliseconds(6000));
-    
-    dr.stop_recording();
+    std::this_thread::sleep_for(std::chrono::milliseconds(test_time_ms));
     dr.write_reg(TIMING_REG_BASE + 0x0, 1);
+    sleep(2);
+    dr.stop_recording();
+    
 
     printf("Expected Data Rate - %.2f MBps Per Channel, Total %.2f\n", expected_data_rate, expected_data_rate * NUM_DMA_CH);
 
 
-}
+}

pcie_driver/Makefile

@@ -0,0 +1,31 @@
+BINARY     := drexpcie_module
+KERNEL      := /lib/modules/$(shell uname -r)/build
+ARCH        := x86
+C_FLAGS     := -Wall
+KMOD_DIR    := $(shell pwd)
+TARGET_PATH := /lib/modules/$(shell uname -r)/kernel/drivers/char
+
+OBJECTS := \
+	drexpcie.o \
+	drexdma.o \
+	drexchar.o \
+
+ccflags-y += $(C_FLAGS)
+
+obj-m += $(BINARY).o
+
+$(BINARY)-y := $(OBJECTS)
+
+$(BINARY).ko:
+	make -C $(KERNEL) M=$(KMOD_DIR) modules
+
+install:
+	cp $(BINARY).ko $(TARGET_PATH)
+	depmod -a
+
+uninstall:
+	rm $(TARGET_PATH)/$(BINARY).ko
+	depmod -a
+
+clean:
+	make -C $(KERNEL) M=$(KMOD_DIR) clean

pcie_driver/drex.h

@@ -0,0 +1,18 @@
+#ifndef DREX_H_
+#define DREX_H_
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
+/* This is a "private" data structure */
+/* You can store there any data that should be passed between driver's functions */
+struct drexpcie_driver_priv {
+   struct pci_dev *pdev;
+   unsigned long mem_start;
+   unsigned long mem_len;   
+   u8 __iomem *bar0_mem;
+};
+
+#endif

pcie_driver/drexchar.c

@@ -0,0 +1,292 @@
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/fs.h>
+
+#include <linux/iomap.h>
+
+#include "drexchar.h"
+#include "drexdma.h"
+
+#define MAX_DEV 16
+
+static int drexpcie_open(struct inode *inode, struct file *file);
+static int drexpcie_release(struct inode *inode, struct file *file);
+static int drexpcie_mmap(struct file *file, struct vm_area_struct *vma);
+static long drexpcie_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
+static ssize_t drexpcie_read(struct file *file, char __user *buf, size_t count, loff_t *offset);
+static ssize_t drexpcie_write(struct file *file, const char __user *buf, size_t count, loff_t *offset);
+
+static const struct file_operations drexpcie_fops = {
+	.owner      = THIS_MODULE,
+	.open       = drexpcie_open,
+	.release    = drexpcie_release,
+   .mmap       = drexpcie_mmap,   
+	.unlocked_ioctl = drexpcie_ioctl,
+	.read       = drexpcie_read,
+	.write      = drexpcie_write
+};
+
+
+struct drexpcie_device_data {
+	struct device* dev;
+	struct cdev cdev;
+   uint32_t type;
+   uint32_t offset;
+};
+
+
+static int dev_major = 0;
+static struct class *drexpcie_class = NULL;
+static struct drexpcie_device_data drexpcie_dev_data[MAX_DEV];
+static struct drexpcie_driver_priv* driv_access = NULL;
+
+static int drexpcie_uevent(const struct device *dev, struct kobj_uevent_env *env)
+{
+	add_uevent_var(env, "DEVMODE=%#o", 0666);
+
+	return 0;
+}
+
+int drexpcie_chardev_create(struct drexpcie_driver_priv *driv_priv)
+{
+	int err, i;
+	dev_t dev;
+
+   char device_string[64];
+
+   int pl_count = 0;
+   int dma_count = 0;
+
+   driv_access = driv_priv;
+
+   err = alloc_chrdev_region(&dev, 0, MAX_DEV, "drexpcie");
+
+	dev_major = MAJOR(dev);
+
+	// drexpcie_class = class_create(THIS_MODULE, "drexpcie-dev");
+   drexpcie_class = class_create("drexpcie-dev");
+
+	drexpcie_class->dev_uevent = drexpcie_uevent;
+
+	for (i = 0; i < MAX_DEV; i++) {
+      drexpcie_dev_data[i].type = ioread32(driv_access->bar0_mem+(i*4)*4);
+      if (drexpcie_dev_data[i].type == 0x10000) {
+         snprintf(device_string,sizeof(device_string),"drexpl%d",pl_count);  
+         pl_count++;       
+      }
+      else if (drexpcie_dev_data[i].type == 0x20000) {
+         snprintf(device_string,sizeof(device_string),"drexdma%d",dma_count);
+         dma_count++;
+      }
+      else {
+         drexpcie_dev_data[i].type = 0;
+         break;
+      }
+
+      // save the offset of the device area;
+      drexpcie_dev_data[i].offset = ioread32(driv_access->bar0_mem+(i*4+1)*4);
+
+		cdev_init(&drexpcie_dev_data[i].cdev, &drexpcie_fops);
+		drexpcie_dev_data[i].cdev.owner = THIS_MODULE;
+		cdev_add(&drexpcie_dev_data[i].cdev, MKDEV(dev_major, i), 1);
+      
+		drexpcie_dev_data[i].dev = device_create(drexpcie_class, NULL, MKDEV(dev_major, i), NULL, "%s",device_string);
+
+	}
+
+	return 0;
+}
+
+int drexpcie_chardev_destroy(void)
+{
+	int i;
+
+	for (i = 0; i < MAX_DEV; i++) {
+		device_destroy(drexpcie_class, MKDEV(dev_major, i));
+	}
+
+	class_unregister(drexpcie_class);
+	class_destroy(drexpcie_class);
+
+	unregister_chrdev_region(MKDEV(dev_major, 0), MINORMASK);
+
+	return 0;
+}
+
+
+static int drexpcie_open(struct inode *inode, struct file *file)
+{
+	struct drexpcie_device_priv* drexpcie_priv;
+	unsigned int minor = iminor(inode);
+
+	drexpcie_priv = kzalloc(sizeof(struct drexpcie_device_priv), GFP_KERNEL);
+	drexpcie_priv->chnum = minor;
+	drexpcie_priv->driv_priv = driv_access;
+//   drexpcie_priv->dev = &(drexpcie_dev_data[drexpcie_priv->chnum].pdev->dev);
+   drexpcie_priv->type = drexpcie_dev_data[drexpcie_priv->chnum].type;
+   drexpcie_priv->base_mem = driv_access->bar0_mem +  drexpcie_dev_data[drexpcie_priv->chnum].offset;
+
+   drexpcie_priv->num_bufs = 512;
+   drexpcie_priv->num_bytes = 4194304;
+   drexpcie_priv->valid_bufs = 0;
+
+   drexpcie_priv->bufPtr = NULL;
+   drexpcie_priv->dmaPtr = (dma_addr_t *) NULL;    
+
+	file->private_data = drexpcie_priv;
+
+	return 0;
+}
+
+static int drexpcie_release(struct inode *inode, struct file *file)
+{
+	struct drexpcie_device_priv* drexpcie_priv = file->private_data;
+
+	kfree(drexpcie_priv);
+
+	drexpcie_priv = NULL;
+
+	return 0;
+}
+
+static int drexpcie_mmap(struct file *file, struct vm_area_struct *vma)
+{
+   struct drexpcie_device_priv* drexpcie_priv = file->private_data;
+   int    ret;
+
+   // DMA doesn't support mmap
+   if (drexpcie_priv->type == 0x20000) return -EINVAL; 
+
+   vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+    
+   ret = io_remap_pfn_range(vma, vma->vm_start, ((unsigned long) drexpcie_priv->driv_priv->mem_start) >> PAGE_SHIFT, vma->vm_end - vma->vm_start, vma->vm_page_prot);
+   if (ret != 0) {
+      printk(KERN_ERR "Error in calling remap_pfn_range: returned %d\n", ret);
+      return -EAGAIN;
+   }
+    
+	 return 0;
+}
+
+static long drexpcie_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	struct drexpcie_device_priv* drexpcie_priv = file->private_data;
+   drexpcie_ioctl_t drexpcie_ioctl;
+
+   // uint32_t temp;
+
+   if (copy_from_user(&drexpcie_ioctl, (drexpcie_ioctl_t *)arg,
+                       sizeof(drexpcie_ioctl_t))) {
+      return -EACCES;
+   } 
+
+   printk("drexpcie[%d]: Received IOCTL cmd=%d\n", drexpcie_priv->chnum,  drexpcie_ioctl.cmd);
+
+   switch (drexpcie_ioctl.cmd) {
+      case DREXDMA_DMA_INIT:
+         return dma_init(drexpcie_priv);
+         break;
+
+      case DREXDMA_DMA_CLEAR:
+         return dma_clear(drexpcie_priv);
+         break;         
+
+      case DREXDMA_DMA_START:
+         return dma_start(drexpcie_priv);
+         break;
+               
+      case DREXDMA_DMA_STOP:
+         return dma_stop(drexpcie_priv);
+         break;
+
+      case DREXDMA_SET_NUM_BUFS:
+         drexpcie_priv->num_bufs = drexpcie_ioctl.value;
+         break;
+
+      case DREXDMA_SET_NUM_BYTES:
+         drexpcie_priv->num_bytes = drexpcie_ioctl.value;
+         break;
+
+      case DREXDMA_GET_NUM_BUFS:
+         drexpcie_ioctl.value = drexpcie_priv->num_bufs;
+         if (copy_to_user((drexpcie_ioctl_t *)arg, &drexpcie_ioctl, sizeof(drexpcie_ioctl_t))) {
+            return -EACCES;
+         }
+         break;
+
+      case DREXDMA_GET_NUM_BYTES:
+         drexpcie_ioctl.value = drexpcie_priv->num_bytes;
+         if (copy_to_user((drexpcie_ioctl_t *)arg, &drexpcie_ioctl, sizeof(drexpcie_ioctl_t))) {
+            return -EACCES;
+         }
+         break;    
+
+      case DREXDMA_GET_FREE_BUFS:
+         drexpcie_ioctl.value = ioread32(drexpcie_priv->base_mem + DREXDMA_OFFSET_STAT + 0x8);
+         if (copy_to_user((drexpcie_ioctl_t *)arg, &drexpcie_ioctl, sizeof(drexpcie_ioctl_t))) {
+            return -EACCES;
+         }
+         break;                 
+
+      default:
+         printk("drexpcie[%d]: error, invalid IOCTL cmd\n", drexpcie_priv->chnum);
+         return -EINVAL;
+    }
+
+	return 0;
+}
+
+static ssize_t drexpcie_read(struct file *file, char __user *buf, size_t count, loff_t *offset)
+{
+   struct drexpcie_device_priv* drexpcie_priv = file->private_data;
+
+   uint32_t temp[3];
+   uint32_t dma_index;
+
+   // read status register to determine is something is in the complete queue
+   temp[0] = ioread32(drexpcie_priv->base_mem + DREXDMA_OFFSET_STAT+0xC);
+
+   // if bit 0 is high, FIFO is empty return 0 count value;
+   if (temp[0] & 0x01) {
+      count = 0;
+   }
+   // else read 72 bit FIFO value;  value is popped after MSW read;
+   else {
+      temp[0] = ioread32(drexpcie_priv->base_mem + DREXDMA_OFFSET_FIFO);
+      // temp[1] = ioread32(drexpcie_priv->base_mem + DREXDMA_OFFSET_FIFO+4);
+      temp[2] = ioread32(drexpcie_priv->base_mem + DREXDMA_OFFSET_FIFO+8);
+      
+      // determine which buffer index;
+      dma_index = temp[0] & 0x000001FF;
+
+      // determine amount of data in buffer;
+      count = (temp[0] & 0xFFFFFE00) >> 9;
+
+      //using dma_index, copy correct buffer to user space 
+      if (copy_to_user(buf, drexpcie_priv->bufPtr[dma_index], count)) {
+         count = 0;
+      }      
+   
+      // create new LSW using index and size
+      temp[0] = (((drexpcie_priv->num_bytes) & 0x7FFFFF) << 9);
+      temp[0] |= (((dma_index) & 0x000001FF));
+
+      // write now unused buffer back to the available queue
+      // If using loop mode dont need to write buffers back in
+      // iowrite32(temp[0], drexpcie_priv->base_mem + DREXDMA_OFFSET_FIFO);
+      // iowrite32(temp[1], drexpcie_priv->base_mem + DREXDMA_OFFSET_FIFO+4);
+      // iowrite32(temp[2], drexpcie_priv->base_mem + DREXDMA_OFFSET_FIFO+8);     
+
+   }
+
+	return count;
+}
+
+static ssize_t drexpcie_write(struct file *file, const char __user *buf, size_t count, loff_t *offset)
+{
+	return count;
+}
+

pcie_driver/drexchar.h

@@ -0,0 +1,48 @@
+
+#ifndef DREXCHAR_H
+#define DREXCHAR_H
+
+#include "drex.h"
+
+#define DREXDMA_DMA_INIT             0
+#define DREXDMA_DMA_CLEAR            1
+#define DREXDMA_DMA_START            2
+#define DREXDMA_DMA_STOP             3
+#define DREXDMA_SET_NUM_BUFS         4
+#define DREXDMA_SET_NUM_BYTES        5
+#define DREXDMA_GET_NUM_BUFS         6
+#define DREXDMA_GET_NUM_BYTES        7
+#define DREXDMA_GET_FREE_BUFS        8
+
+
+typedef struct {
+   unsigned int cmd;
+   unsigned int offset;
+   unsigned int value;
+} drexpcie_ioctl_t;  
+
+
+struct drexpcie_device_priv {
+	uint8_t chnum;
+	struct drexpcie_driver_priv* driv_priv;
+   
+   uint32_t type;
+   u8 __iomem *base_mem;
+
+   // Parameters used to allocate dma buffers
+   uint32_t num_bufs;
+   uint32_t valid_bufs;
+   uint32_t num_bytes;
+
+   // Physical memory address returned by dma_alloc_coherent
+   dma_addr_t *dmaPtr;
+                    
+   // Virtual memory address returned by dma_alloc_coherent
+   void  **bufPtr;
+
+};
+
+int drexpcie_chardev_create(struct drexpcie_driver_priv *driv_priv);
+int drexpcie_chardev_destroy(void);
+
+#endif

pcie_driver/drexdma.c

@@ -0,0 +1,158 @@
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/fs.h>
+
+#include <linux/dma-mapping.h>
+
+#include "drexdma.h"
+
+
+
+// Initial DMA buffers function
+int init_dma_buffers(struct drexpcie_device_priv *drexpcie_priv)
+{
+   int buffer_index;
+
+   // allocate an array for the buffer pointers (kernel space)
+   drexpcie_priv->bufPtr = kzalloc(drexpcie_priv->num_bufs*sizeof(void *),GFP_KERNEL);
+   if (drexpcie_priv->bufPtr == NULL) {
+      printk("drexpcie[%d]: error, failed to alloc bufPtr memory\n", drexpcie_priv->chnum);
+      return -ENOMEM;
+   }
+
+   // allocate an array for the dma pointers (physical address)
+   drexpcie_priv->dmaPtr = kzalloc(drexpcie_priv->num_bufs*sizeof(dma_addr_t),GFP_KERNEL);
+   if (drexpcie_priv->dmaPtr == NULL) {
+      printk("drexpcie[%d]: error, failed to alloc dmaPtr memory\n", drexpcie_priv->chnum);
+      return -ENOMEM;
+   }
+
+   // loop through the total number of desired buffer and attempt to allocate;
+   // This will populate both the bufPtr and dmaPtr
+   for (buffer_index = 0; buffer_index < drexpcie_priv->num_bufs; buffer_index++) {
+      drexpcie_priv->bufPtr[buffer_index] = dma_alloc_coherent(&(drexpcie_priv->driv_priv->pdev->dev), drexpcie_priv->num_bytes, &drexpcie_priv->dmaPtr[buffer_index], GFP_KERNEL);
+      printk("Allocating Memory: %p, %llX\n",drexpcie_priv->bufPtr[buffer_index],drexpcie_priv->dmaPtr[buffer_index]);
+            
+      if (drexpcie_priv->bufPtr[buffer_index] == NULL) {
+         printk("drexpcie[%d]: warning, DMA mem allocation failed at %d buffers\n", drexpcie_priv->chnum, buffer_index);
+         break;
+      }
+   } 
+
+   drexpcie_priv->valid_bufs = buffer_index;  
+
+   return 0;
+}
+
+// Release (free) DMA buffers function
+void release_dma_buffers(struct drexpcie_device_priv *drexpcie_priv)
+{
+   int buffer_index;
+
+   if (drexpcie_priv->bufPtr) {
+      for (buffer_index=0; buffer_index<drexpcie_priv->valid_bufs; buffer_index++) {
+         if (drexpcie_priv->bufPtr[buffer_index]) {
+            printk("Freeing Memory: %p, %llX\n",drexpcie_priv->bufPtr[buffer_index],drexpcie_priv->dmaPtr[buffer_index]);
+            dma_free_coherent(&(drexpcie_priv->driv_priv->pdev->dev), drexpcie_priv->num_bytes , drexpcie_priv->bufPtr[buffer_index], drexpcie_priv->dmaPtr[buffer_index]);
+            
+            // This is unnecessary, but cleaner
+            drexpcie_priv->bufPtr[buffer_index] = NULL;
+            drexpcie_priv->dmaPtr[buffer_index] = (dma_addr_t) NULL;
+         }
+      }
+      kfree(drexpcie_priv->bufPtr);
+      drexpcie_priv->bufPtr = NULL;
+   }
+
+   if (drexpcie_priv->dmaPtr) {
+      kfree(drexpcie_priv->dmaPtr);
+      drexpcie_priv->dmaPtr = NULL;
+   }
+
+   drexpcie_priv->valid_bufs = 0;
+
+}
+
+// Start the DMA function
+int dma_init(struct drexpcie_device_priv *drexpcie_priv)
+{
+   int i;
+   int ret;
+   uint32_t temp[3];
+   uint64_t temp64;
+
+   // set reset bits
+   iowrite32(0x00000007, drexpcie_priv->base_mem+DREXDMA_OFFSET_CTRL);
+                      
+   // clears queues if dma_start is called multiple times.
+   release_dma_buffers(drexpcie_priv);
+
+   ret = init_dma_buffers(drexpcie_priv);
+
+   if (ret) {
+      release_dma_buffers(drexpcie_priv);
+      return ret;
+   }
+   
+   // clear reset bits
+   iowrite32(0x00000000, drexpcie_priv->base_mem+DREXDMA_OFFSET_CTRL);
+       
+   // writes buffer to the available FIFO
+   printk("drexpcie[%d]: writing %d buffers to FIFO\n", drexpcie_priv->chnum, drexpcie_priv->valid_bufs );
+   for (i = 0; i < drexpcie_priv->valid_bufs; i++) {
+      temp64 = drexpcie_priv->dmaPtr[i];
+      temp[0] = (((drexpcie_priv->num_bytes) & 0x7FFFFF) << 9);
+      temp[0] |= (((i) & 0x000001FF));
+      temp[1] = temp64 & 0xFFFFFFFF;
+      temp[2] = (temp64 >> 32) & 0x000000FF;
+
+      printk("drexpcie[%d]: writing %x %x %x to FIFO\n", drexpcie_priv->chnum, temp[2],temp[1],temp[0]);
+      iowrite32(temp[0], drexpcie_priv->base_mem+DREXDMA_OFFSET_FIFO);
+      iowrite32(temp[1], drexpcie_priv->base_mem+DREXDMA_OFFSET_FIFO+4);
+      iowrite32(temp[2], drexpcie_priv->base_mem+DREXDMA_OFFSET_FIFO+8);            
+   }
+   
+   // Enable Loop Mode
+   printk("drexpcie[%d]: enabling loop mode\n", drexpcie_priv->chnum);
+   iowrite32(1, drexpcie_priv->base_mem+DREXDMA_OFFSET_CTRL+4);
+
+   // Enable DMA Engine
+   // iowrite32(0x00000100, drexpcie_privDREXDMA_OFFSET_CTRL);
+
+   return 0;
+}
+
+int dma_clear(struct drexpcie_device_priv *drexpcie_priv)
+{
+
+   // set reset bits
+   iowrite32(0x00000007, drexpcie_priv->base_mem+DREXDMA_OFFSET_CTRL);
+      
+   // Disable Loop Mode
+   iowrite32(0, drexpcie_priv->base_mem+DREXDMA_OFFSET_CTRL+4);
+
+   release_dma_buffers(drexpcie_priv);
+ 
+   return 0;
+}
+
+int dma_start(struct drexpcie_device_priv *drexpcie_priv)
+{
+   
+   // Enable DMA Engine
+   iowrite32(0x00000100, drexpcie_priv->base_mem+DREXDMA_OFFSET_CTRL);
+ 
+   return 0;
+}
+
+int dma_stop(struct drexpcie_device_priv *drexpcie_priv)
+{
+   
+   // Disable DMA Engine
+   iowrite32(0x00000000, drexpcie_priv->base_mem+DREXDMA_OFFSET_CTRL);
+
+   return 0;
+}

pcie_driver/drexdma.h

@@ -0,0 +1,20 @@
+
+#ifndef DREXDMA_H
+#define DREXDMA_H
+
+#include "drexchar.h"
+
+#define DREXDMA_OFFSET_CTRL 0x00
+#define DREXDMA_OFFSET_STAT 0x10
+#define DREXDMA_OFFSET_FIFO 0x20
+
+int init_dma_buffers(struct drexpcie_device_priv *drexpcie_priv);
+void release_dma_buffers(struct drexpcie_device_priv *drexpcie_priv);
+
+int dma_init(struct drexpcie_device_priv *drexpcie_priv);
+int dma_clear(struct drexpcie_device_priv *drexpcie_priv);
+int dma_start(struct drexpcie_device_priv *drexpcie_priv);
+int dma_stop(struct drexpcie_device_priv *drexpcie_priv);
+
+
+#endif

pcie_driver/drexpcie.c

@@ -0,0 +1,189 @@
+
+#include "drex.h"
+#include "drexchar.h"
+
+#define DRIVER_NAME "drexpcie"
+
+/* This sample driver supports device with VID = 0x010F, and PID = 0x0F0E*/
+static struct pci_device_id drexpcie_driver_id_table[] = {
+   { PCI_DEVICE(0x10EE, 0x903F) },
+   {0,}
+};
+
+MODULE_DEVICE_TABLE(pci, drexpcie_driver_id_table);
+
+static int drexpcie_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
+static void drexpcie_driver_remove(struct pci_dev *pdev);
+
+/* Driver registration structure */
+static struct pci_driver drexpcie_driver = {
+   .name = DRIVER_NAME,
+   .id_table = drexpcie_driver_id_table,
+   .probe = drexpcie_driver_probe,
+   .remove = drexpcie_driver_remove
+};
+
+
+static int __init drexpcie_driver_init(void)
+{
+   /* Register new PCI driver */
+   int result = pci_register_driver(&drexpcie_driver);
+   if (result < 0) {
+      // This print will tell you exactly why it failed
+      pr_err("pci_register_driver failed with error: %d\n", result);
+      return result; 
+   }
+
+   pr_info("Xilinx custom driver registered successfully!\n");   
+
+   return result;
+}
+
+static void __exit drexpcie_driver_exit(void)
+{
+   /* Unregister */
+   pci_unregister_driver(&drexpcie_driver);
+}
+
+void release_device(struct pci_dev *pdev)
+{
+   /* Disable IRQ #42*/
+//    free_irq(42, pdev);
+   /* Free memory region */
+   pci_release_region(pdev, pci_select_bars(pdev, IORESOURCE_MEM));
+   /* And disable device */
+   pci_disable_device(pdev);
+}
+
+/* */
+
+static irqreturn_t irq_handler(int irq, void *cookie)
+{
+   (void) cookie;
+   printk("Handle IRQ #%d\n", irq);
+   return IRQ_HANDLED;
+}
+
+/* Reqest interrupt and setup handler */
+int set_interrupts(struct pci_dev *pdev)
+{
+   /* We want MSI interrupt, 3 lines (just an example) */
+   int ret = pci_alloc_irq_vectors(pdev, 3, 3, PCI_IRQ_MSI);
+
+   if (ret < 0) {
+      return ret;
+   }
+
+   /* Request IRQ #42 */
+   return request_threaded_irq(42, irq_handler, NULL, 0, "TEST IRQ", pdev);
+}
+
+
+
+/* This function is called by the kernel */
+static int drexpcie_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+   int bar, err;
+   u16 vendor, device;
+//    unsigned long mmio_start,mmio_len;
+   struct drexpcie_driver_priv *drv_priv;
+
+   printk("drexpcie probe\n");
+
+   /* Let's read data from the PCI device configuration registers */
+   pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
+   pci_read_config_word(pdev, PCI_DEVICE_ID, &device);
+
+   printk(KERN_INFO "Device vid: 0x%X pid: 0x%X\n", vendor, device);
+
+   /* Request IO BAR */
+   bar = pci_select_bars(pdev, IORESOURCE_MEM);
+
+   /* Enable device memory */
+   err = pci_enable_device_mem(pdev);
+
+   if (err) {
+      return err;
+   }
+
+   /* Request memory region for the BAR */
+   err = pci_request_region(pdev, bar, DRIVER_NAME);
+
+   if (err) {
+      pci_disable_device(pdev);
+      return err;
+   }
+   
+   pci_set_master(pdev);
+
+   if (dma_set_mask_and_coherent(&(pdev->dev), DMA_BIT_MASK(40))) {
+      printk("dma_set_mask_and_coherent error\n");
+   }
+
+   /* Allocate memory for the driver private data */
+   drv_priv = kzalloc(sizeof(struct drexpcie_driver_priv), GFP_KERNEL);
+
+   if (!drv_priv) {
+      release_device(pdev);
+      return -ENOMEM;
+   }
+
+   drv_priv->pdev = pdev;
+
+   /* Get start and stop memory offsets */
+   drv_priv->mem_start = pci_resource_start(pdev, 0);
+   drv_priv->mem_len = pci_resource_len(pdev, 0);
+
+   printk(KERN_INFO "Resource Start: 0x%lX length: 0x%lX\n", drv_priv->mem_start, drv_priv->mem_len);
+
+   /* Remap BAR to the local pointer */
+   drv_priv->bar0_mem = ioremap(drv_priv->mem_start, drv_priv->mem_len);
+
+   if (!drv_priv->bar0_mem) {
+      release_device(pdev);
+      return -EIO;
+   }
+
+   drexpcie_chardev_create(drv_priv);
+
+   /* Set driver private data */
+   /* Now we can access mapped "bar0_mem" from the any driver's function */
+   pci_set_drvdata(pdev, drv_priv);
+
+   return 0;
+    
+//    return set_interrupts(pdev);
+}
+
+/* Clean up */
+static void drexpcie_driver_remove(struct pci_dev *pdev)
+{
+   struct drexpcie_driver_priv *drv_priv = pci_get_drvdata(pdev);
+
+   drexpcie_chardev_destroy();
+
+   if (drv_priv) {
+      if (drv_priv->bar0_mem) {
+         iounmap(drv_priv->bar0_mem);
+      }
+
+      pci_free_irq_vectors(pdev);
+
+      kfree(drv_priv);
+      pci_set_drvdata(pdev, NULL); 
+   }
+
+   // release_device(pdev);
+   pci_release_region(pdev, 0); 
+   pci_disable_device(pdev);    
+
+}
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("");
+MODULE_DESCRIPTION("DREX PCIe driver");
+MODULE_VERSION("0.1");
+
+module_init(drexpcie_driver_init);
+module_exit(drexpcie_driver_exit);
+

project_1.srcs/constrs_1/constraints.xdc

@@ -1,50 +1,181 @@
 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 
-set_property PACKAGE_PIN M9 [get_ports {leds[0]}]
-set_property PACKAGE_PIN K8 [get_ports {leds[1]}]
-set_property PACKAGE_PIN L8 [get_ports {leds[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
+#set_property PACKAGE_PIN M9 [get_ports {leds[0]}]
+#set_property PACKAGE_PIN K8 [get_ports {leds[1]}]
+#set_property PACKAGE_PIN L8 [get_ports {leds[2]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
 
-set_property PACKAGE_PIN N8 [get_ports uart_rxd]
-set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd]
+#set_property PACKAGE_PIN N8 [get_ports uart_rxd]
+#set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd]
 
-set_property PACKAGE_PIN N9 [get_ports uart_txd]
-set_property IOSTANDARD LVCMOS33 [get_ports uart_txd]
+#set_property PACKAGE_PIN N9 [get_ports uart_txd]
+#set_property IOSTANDARD LVCMOS33 [get_ports uart_txd]
 
-set_property PACKAGE_PIN AJ9 [get_ports sys_clk_p]
-set_property PACKAGE_PIN AK9 [get_ports sys_clk_n]
+set_property PACKAGE_PIN AP19 [get_ports sys_clk_p]
+set_property PACKAGE_PIN AR19 [get_ports sys_clk_n]
 set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p]
 set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n]
-create_clock -period 5.000 -name sys_clk_clk_p [get_ports sys_clk_p]
+create_clock -period 10.000 -name sys_clk_clk_p [get_ports sys_clk_p]
 
-set_property PACKAGE_PIN M8 [get_ports fan_pwm]
-set_property IOSTANDARD LVCMOS33 [get_ports fan_pwm]
+#set_property PACKAGE_PIN M8 [get_ports fan_pwm]
+#set_property IOSTANDARD LVCMOS33 [get_ports fan_pwm]
 
 #-------------------------------------------
 # PCIE
 #-------------------------------------------
-set_property PACKAGE_PIN AD8 [get_ports pcie_ref_clk_p]
+set_property PACKAGE_PIN AB27 [get_ports pcie_ref_clk_p]
 create_clock -period 10.000 -name pcie_ref_clk_p -waveform {0.000 5.000} [get_ports pcie_ref_clk_p]
 
-set_property PACKAGE_PIN AP4 [get_ports {pcie_mgt_rxp[0]}]
-set_property PACKAGE_PIN AN2 [get_ports {pcie_mgt_rxp[1]}]
-set_property PACKAGE_PIN AL2 [get_ports {pcie_mgt_rxp[2]}]
-set_property PACKAGE_PIN AK4 [get_ports {pcie_mgt_rxp[3]}]
-set_property PACKAGE_PIN AJ2 [get_ports {pcie_mgt_rxp[4]}]
-set_property PACKAGE_PIN AG2 [get_ports {pcie_mgt_rxp[5]}]
-set_property PACKAGE_PIN AF4 [get_ports {pcie_mgt_rxp[6]}]
-set_property PACKAGE_PIN AE2 [get_ports {pcie_mgt_rxp[7]}]
+set_property PACKAGE_PIN AA38 [get_ports {pcie_mgt_rxp[8]}]
+set_property PACKAGE_PIN AB36 [get_ports {pcie_mgt_rxp[9]}]
+set_property PACKAGE_PIN AC38 [get_ports {pcie_mgt_rxp[10]}]
+set_property PACKAGE_PIN AD36 [get_ports {pcie_mgt_rxp[11]}]
+set_property PACKAGE_PIN AE38 [get_ports {pcie_mgt_rxp[12]}]
+set_property PACKAGE_PIN AF36 [get_ports {pcie_mgt_rxp[13]}]
+set_property PACKAGE_PIN AG38 [get_ports {pcie_mgt_rxp[14]}]
+set_property PACKAGE_PIN AH36 [get_ports {pcie_mgt_rxp[15]}]
 
-set_property PACKAGE_PIN AN6 [get_ports {pcie_mgt_txp[0]}]
-set_property PACKAGE_PIN AM4 [get_ports {pcie_mgt_txp[1]}]
-set_property PACKAGE_PIN AL6 [get_ports {pcie_mgt_txp[2]}]
-set_property PACKAGE_PIN AJ6 [get_ports {pcie_mgt_txp[3]}]
-set_property PACKAGE_PIN AH4 [get_ports {pcie_mgt_txp[4]}]
-set_property PACKAGE_PIN AG6 [get_ports {pcie_mgt_txp[5]}]
-set_property PACKAGE_PIN AE6 [get_ports {pcie_mgt_txp[6]}]
-set_property PACKAGE_PIN AD4 [get_ports {pcie_mgt_txp[7]}]
+set_property PACKAGE_PIN N38 [get_ports {pcie_mgt_rxp[0]}]
+set_property PACKAGE_PIN L33 [get_ports {pcie_mgt_txp[0]}]
+set_property PACKAGE_PIN P36 [get_ports {pcie_mgt_rxp[1]}]
+set_property PACKAGE_PIN M31 [get_ports {pcie_mgt_txp[1]}]
+set_property PACKAGE_PIN R38 [get_ports {pcie_mgt_rxp[2]}]
+set_property PACKAGE_PIN N33 [get_ports {pcie_mgt_txp[2]}]
+set_property PACKAGE_PIN T36 [get_ports {pcie_mgt_rxp[3]}]
+set_property PACKAGE_PIN P31 [get_ports {pcie_mgt_txp[3]}]
+set_property PACKAGE_PIN U38 [get_ports {pcie_mgt_rxp[4]}]
+set_property PACKAGE_PIN R33 [get_ports {pcie_mgt_txp[4]}]
+set_property PACKAGE_PIN V36 [get_ports {pcie_mgt_rxp[5]}]
+set_property PACKAGE_PIN T31 [get_ports {pcie_mgt_txp[5]}]
+set_property PACKAGE_PIN W38 [get_ports {pcie_mgt_rxp[6]}]
+set_property PACKAGE_PIN U33 [get_ports {pcie_mgt_txp[6]}]
+set_property PACKAGE_PIN Y36 [get_ports {pcie_mgt_rxp[7]}]
+set_property PACKAGE_PIN V31 [get_ports {pcie_mgt_txp[7]}]
+set_property PACKAGE_PIN W33 [get_ports {pcie_mgt_txp[8]}]
+set_property PACKAGE_PIN AB36 [get_ports {pcie_mgt_txp[9]}]
+set_property PACKAGE_PIN AA33 [get_ports {pcie_mgt_txp[10]}]
+set_property PACKAGE_PIN AB31 [get_ports {pcie_mgt_txp[11]}]
+set_property PACKAGE_PIN AC33 [get_ports {pcie_mgt_txp[12]}]
+set_property PACKAGE_PIN AD31 [get_ports {pcie_mgt_txp[13]}]
+set_property PACKAGE_PIN AE33 [get_ports {pcie_mgt_txp[14]}]
+set_property PACKAGE_PIN AF31 [get_ports {pcie_mgt_txp[15]}]
 
-set_property PACKAGE_PIN AA20 [get_ports pcie_rst_n]
-set_property IOSTANDARD LVCMOS18 [get_ports pcie_rst_n]
+set_property PACKAGE_PIN D13 [get_ports pcie_rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_rst_n]
 
 
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 1 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list design_1_i/xdma_0/inst/pcie4_ip_i/inst/design_1_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/CLK_USERCLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 1 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {design_1_i/pcie_m_axi1_bvalid[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 1 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {design_1_i/pcie_m_axi1_wvalid[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 1 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {design_1_i/pcie_m_axi1_awvalid[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 1 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {design_1_i/pcie_m_axi1_wready[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {design_1_i/pcie_m_axi1_bready[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {design_1_i/pcie_m_axi1_awready[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {design_1_i/pcie_m_axi0_wvalid[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 1 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {design_1_i/pcie_m_axi0_bvalid[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 1 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {design_1_i/pcie_m_axi0_wready[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 1 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {design_1_i/pcie_m_axi0_bready[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {design_1_i/pcie_m_axi0_awvalid[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {design_1_i/pcie_m_axi1_wlast[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {design_1_i/pcie_m_axi0_awready[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {design_1_i/pcie_m_axi0_wlast[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 1 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_WVALID]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 1 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_WREADY]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 1 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_WLAST]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 1 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_BVALID]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 1 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_BREADY]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 1 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_AWVALID]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 1 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_AWREADY]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 1 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list start_of_pulse]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 1 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {pcie_dma_axis\\.tvalid}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 1 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {pcie_dma_axis\\.tready}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list {pcie_dma_axis\\.tlast}]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets clk]

project_1.srcs/sources_1/bd/design_1/design_1.bda

@@ -23,9 +23,27 @@
   <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
   <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
     <node id="n0">
-      <data key="BA">0x0080110000</data>
+      <data key="BA">0x80010000</data>
       <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x008011FFFF</data>
+      <data key="HA">0x8001FFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">Data</data>
+      <data key="MX">/microblaze_0</data>
+      <data key="MI">M_AXI_DP</data>
+      <data key="MS">SEG_axil_util_Reg</data>
+      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
+      <data key="TM">data</data>
+      <data key="SX">/</data>
+      <data key="SI">axil_util</data>
+      <data key="SS">Reg</data>
+      <data key="SV">::design_1_imp:</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n1">
+      <data key="BA">0x0080020000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0x008002FFFF</data>
       <data key="HP">C_HIGHADDR</data>
       <data key="MA">M_AXI_B</data>
       <data key="MX">/xdma_0</data>
@@ -40,43 +58,61 @@
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n1">
-      <data key="BA">0x81010000</data>
+    <node id="n2">
+      <data key="BA">0x40000000</data>
       <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x8101FFFF</data>
+      <data key="HA">0x4000FFFF</data>
       <data key="HP">C_HIGHADDR</data>
       <data key="MA">Data</data>
       <data key="MX">/microblaze_0</data>
       <data key="MI">M_AXI_DP</data>
-      <data key="MS">SEG_axil_dma_ctrl1_Reg</data>
+      <data key="MS">SEG_axi_timer_0_Reg</data>
+      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
+      <data key="TM">data</data>
+      <data key="SX">/axi_timer_0</data>
+      <data key="SI">S_AXI</data>
+      <data key="SS">Reg</data>
+      <data key="SV">xilinx.com:ip:axi_timer:2.0</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n3">
+      <data key="BA">0x80000000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0x8000FFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">Data</data>
+      <data key="MX">/microblaze_0</data>
+      <data key="MI">M_AXI_DP</data>
+      <data key="MS">SEG_axil_descriptors_Reg</data>
       <data key="MV">xilinx.com:ip:microblaze:11.0</data>
       <data key="TM">data</data>
       <data key="SX">/</data>
-      <data key="SI">axil_dma_ctrl1</data>
+      <data key="SI">axil_descriptors</data>
       <data key="SS">Reg</data>
       <data key="SV">::design_1_imp:</data>
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n2">
-      <data key="BA">0x40030000</data>
+    <node id="n4">
+      <data key="BA">0x0080000000</data>
       <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x4003FFFF</data>
+      <data key="HA">0x008000FFFF</data>
       <data key="HP">C_HIGHADDR</data>
-      <data key="MA">Data</data>
-      <data key="MX">/microblaze_0</data>
-      <data key="MI">M_AXI_DP</data>
-      <data key="MS">SEG_system_management_wiz_0_Reg</data>
-      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
-      <data key="TM">data</data>
-      <data key="SX">/system_management_wiz_0</data>
-      <data key="SI">S_AXI_LITE</data>
+      <data key="MA">M_AXI_B</data>
+      <data key="MX">/xdma_0</data>
+      <data key="MI">M_AXI_B</data>
+      <data key="MS">SEG_axil_descriptors_Reg</data>
+      <data key="MV">xilinx.com:ip:xdma:4.1</data>
+      <data key="TM">both</data>
+      <data key="SX">/</data>
+      <data key="SI">axil_descriptors</data>
       <data key="SS">Reg</data>
-      <data key="SV">xilinx.com:ip:system_management_wiz:1.3</data>
+      <data key="SV">::design_1_imp:</data>
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n3">
+    <node id="n5">
       <data key="BA">0x0000000000</data>
       <data key="BP">axibar_0</data>
       <data key="HA">0xFFFFFFFFFF</data>
@@ -94,25 +130,48 @@
       <data key="TU">memory</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n4">
-      <data key="BA">0x0081010000</data>
+    <node id="n6">
+      <data key="TU">active</data>
+      <data key="VH">2</data>
+      <data key="VT">PM</data>
+    </node>
+    <node id="n7">
+      <data key="BA">0x0000000000</data>
+      <data key="BP">axibar_0</data>
+      <data key="HA">0xFFFFFFFFFF</data>
+      <data key="HP">axibar_highaddr_0</data>
+      <data key="MA">pcie_m_axi3</data>
+      <data key="MX">/</data>
+      <data key="MI">pcie_m_axi3</data>
+      <data key="MS">SEG_xdma_0_BAR0</data>
+      <data key="MV">:::</data>
+      <data key="TM">both</data>
+      <data key="SX">/xdma_0</data>
+      <data key="SI">S_AXI_B</data>
+      <data key="SS">BAR0</data>
+      <data key="SV">xilinx.com:ip:xdma:4.1</data>
+      <data key="TU">memory</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n8">
+      <data key="BA">0x0080010000</data>
       <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x008101FFFF</data>
+      <data key="HA">0x008001FFFF</data>
       <data key="HP">C_HIGHADDR</data>
       <data key="MA">M_AXI_B</data>
       <data key="MX">/xdma_0</data>
       <data key="MI">M_AXI_B</data>
-      <data key="MS">SEG_axil_dma_ctrl1_Reg</data>
+      <data key="MS">SEG_axil_util_Reg</data>
       <data key="MV">xilinx.com:ip:xdma:4.1</data>
       <data key="TM">both</data>
       <data key="SX">/</data>
-      <data key="SI">axil_dma_ctrl1</data>
+      <data key="SI">axil_util</data>
       <data key="SS">Reg</data>
       <data key="SV">::design_1_imp:</data>
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n5">
+    <node id="n9">
       <data key="BA">0x40020000</data>
       <data key="BP">C_BASEADDR</data>
       <data key="HA">0x4002FFFF</data>
@@ -131,32 +190,50 @@
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n6">
-      <data key="BA">0x80100000</data>
+    <node id="n10">
+      <data key="BA">0x80110000</data>
       <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x8010FFFF</data>
+      <data key="HA">0x8011FFFF</data>
       <data key="HP">C_HIGHADDR</data>
       <data key="MA">Data</data>
       <data key="MX">/microblaze_0</data>
       <data key="MI">M_AXI_DP</data>
-      <data key="MS">SEG_axil_util_Reg</data>
+      <data key="MS">SEG_axil_dma_ctrl1_Reg</data>
       <data key="MV">xilinx.com:ip:microblaze:11.0</data>
       <data key="TM">data</data>
       <data key="SX">/</data>
-      <data key="SI">axil_util</data>
+      <data key="SI">axil_dma_ctrl1</data>
       <data key="SS">Reg</data>
       <data key="SV">::design_1_imp:</data>
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n7">
+    <node id="n11">
+      <data key="BA">0x0080130000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0x008013FFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">M_AXI_B</data>
+      <data key="MX">/xdma_0</data>
+      <data key="MI">M_AXI_B</data>
+      <data key="MS">SEG_axil_dma_ctrl3_Reg</data>
+      <data key="MV">xilinx.com:ip:xdma:4.1</data>
+      <data key="TM">both</data>
+      <data key="SX">/</data>
+      <data key="SI">axil_dma_ctrl3</data>
+      <data key="SS">Reg</data>
+      <data key="SV">::design_1_imp:</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n12">
       <data key="BA">0x0000000000</data>
       <data key="BP">axibar_0</data>
       <data key="HA">0xFFFFFFFFFF</data>
       <data key="HP">axibar_highaddr_0</data>
-      <data key="MA">pcie_m_axi0</data>
+      <data key="MA">pcie_m_axi2</data>
       <data key="MX">/</data>
-      <data key="MI">pcie_m_axi0</data>
+      <data key="MI">pcie_m_axi2</data>
       <data key="MS">SEG_xdma_0_BAR0</data>
       <data key="MV">:::</data>
       <data key="TM">both</data>
@@ -167,102 +244,7 @@
       <data key="TU">memory</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n8">
-      <data key="BA">0x0083000000</data>
-      <data key="BP">baseaddr</data>
-      <data key="HA">0x0083FFFFFF</data>
-      <data key="HP">highaddr</data>
-      <data key="MA">M_AXI_B</data>
-      <data key="MX">/xdma_0</data>
-      <data key="MI">M_AXI_B</data>
-      <data key="MS">SEG_xdma_0_CTL0</data>
-      <data key="MV">xilinx.com:ip:xdma:4.1</data>
-      <data key="TM">both</data>
-      <data key="SX">/xdma_0</data>
-      <data key="SI">S_AXI_LITE</data>
-      <data key="SS">CTL0</data>
-      <data key="SV">xilinx.com:ip:xdma:4.1</data>
-      <data key="TU">memory</data>
-      <data key="VT">AC</data>
-    </node>
-    <node id="n9">
-      <data key="BA">0x0081000000</data>
-      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x008100FFFF</data>
-      <data key="HP">C_HIGHADDR</data>
-      <data key="MA">M_AXI_B</data>
-      <data key="MX">/xdma_0</data>
-      <data key="MI">M_AXI_B</data>
-      <data key="MS">SEG_axil_dma_ctrl0_Reg</data>
-      <data key="MV">xilinx.com:ip:xdma:4.1</data>
-      <data key="TM">both</data>
-      <data key="SX">/</data>
-      <data key="SI">axil_dma_ctrl0</data>
-      <data key="SS">Reg</data>
-      <data key="SV">::design_1_imp:</data>
-      <data key="TU">register</data>
-      <data key="VT">AC</data>
-    </node>
-    <node id="n10">
-      <data key="BA">0x0080000000</data>
-      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x008000FFFF</data>
-      <data key="HP">C_HIGHADDR</data>
-      <data key="MA">M_AXI_B</data>
-      <data key="MX">/xdma_0</data>
-      <data key="MI">M_AXI_B</data>
-      <data key="MS">SEG_axil_descriptors_Reg</data>
-      <data key="MV">xilinx.com:ip:xdma:4.1</data>
-      <data key="TM">both</data>
-      <data key="SX">/</data>
-      <data key="SI">axil_descriptors</data>
-      <data key="SS">Reg</data>
-      <data key="SV">::design_1_imp:</data>
-      <data key="TU">register</data>
-      <data key="VT">AC</data>
-    </node>
-    <node id="n11">
-      <data key="VH">2</data>
-      <data key="VM">design_1</data>
-      <data key="VT">VR</data>
-    </node>
-    <node id="n12">
-      <data key="BA">0x81000000</data>
-      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x8100FFFF</data>
-      <data key="HP">C_HIGHADDR</data>
-      <data key="MA">Data</data>
-      <data key="MX">/microblaze_0</data>
-      <data key="MI">M_AXI_DP</data>
-      <data key="MS">SEG_axil_dma_ctrl0_Reg</data>
-      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
-      <data key="TM">data</data>
-      <data key="SX">/</data>
-      <data key="SI">axil_dma_ctrl0</data>
-      <data key="SS">Reg</data>
-      <data key="SV">::design_1_imp:</data>
-      <data key="TU">register</data>
-      <data key="VT">AC</data>
-    </node>
     <node id="n13">
-      <data key="BA">0x80110000</data>
-      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x8011FFFF</data>
-      <data key="HP">C_HIGHADDR</data>
-      <data key="MA">Data</data>
-      <data key="MX">/microblaze_0</data>
-      <data key="MI">M_AXI_DP</data>
-      <data key="MS">SEG_axil_timing_Reg</data>
-      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
-      <data key="TM">data</data>
-      <data key="SX">/</data>
-      <data key="SI">axil_timing</data>
-      <data key="SS">Reg</data>
-      <data key="SV">::design_1_imp:</data>
-      <data key="TU">register</data>
-      <data key="VT">AC</data>
-    </node>
-    <node id="n14">
       <data key="BA">0x0080100000</data>
       <data key="BP">C_BASEADDR</data>
       <data key="HA">0x008010FFFF</data>
@@ -270,17 +252,111 @@
       <data key="MA">M_AXI_B</data>
       <data key="MX">/xdma_0</data>
       <data key="MI">M_AXI_B</data>
-      <data key="MS">SEG_axil_util_Reg</data>
+      <data key="MS">SEG_axil_dma_ctrl0_Reg</data>
       <data key="MV">xilinx.com:ip:xdma:4.1</data>
       <data key="TM">both</data>
       <data key="SX">/</data>
-      <data key="SI">axil_util</data>
+      <data key="SI">axil_dma_ctrl0</data>
+      <data key="SS">Reg</data>
+      <data key="SV">::design_1_imp:</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n14">
+      <data key="BA">0x0080110000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0x008011FFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">M_AXI_B</data>
+      <data key="MX">/xdma_0</data>
+      <data key="MI">M_AXI_B</data>
+      <data key="MS">SEG_axil_dma_ctrl1_Reg</data>
+      <data key="MV">xilinx.com:ip:xdma:4.1</data>
+      <data key="TM">both</data>
+      <data key="SX">/</data>
+      <data key="SI">axil_dma_ctrl1</data>
       <data key="SS">Reg</data>
       <data key="SV">::design_1_imp:</data>
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
     <node id="n15">
+      <data key="BA">0x0080030000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0x008003FFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">M_AXI_B</data>
+      <data key="MX">/xdma_0</data>
+      <data key="MI">M_AXI_B</data>
+      <data key="MS">SEG_axil_data_gen_Reg</data>
+      <data key="MV">xilinx.com:ip:xdma:4.1</data>
+      <data key="TM">both</data>
+      <data key="SX">/</data>
+      <data key="SI">axil_data_gen</data>
+      <data key="SS">Reg</data>
+      <data key="SV">::design_1_imp:</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n16">
+      <data key="BA">0x40010000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0x40010FFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">Data</data>
+      <data key="MX">/microblaze_0</data>
+      <data key="MI">M_AXI_DP</data>
+      <data key="MS">SEG_mdm_1_Reg</data>
+      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
+      <data key="TM">data</data>
+      <data key="SX">/mdm_1</data>
+      <data key="SI">S_AXI</data>
+      <data key="SS">Reg</data>
+      <data key="SV">xilinx.com:ip:mdm:3.2</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n17">
+      <data key="BA">0x40030000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0x4003FFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">Data</data>
+      <data key="MX">/microblaze_0</data>
+      <data key="MI">M_AXI_DP</data>
+      <data key="MS">SEG_system_management_wiz_0_Reg</data>
+      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
+      <data key="TM">data</data>
+      <data key="SX">/system_management_wiz_0</data>
+      <data key="SI">S_AXI_LITE</data>
+      <data key="SS">Reg</data>
+      <data key="SV">xilinx.com:ip:system_management_wiz:1.3</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n18">
+      <data key="BA">0x0080120000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0x008012FFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">M_AXI_B</data>
+      <data key="MX">/xdma_0</data>
+      <data key="MI">M_AXI_B</data>
+      <data key="MS">SEG_axil_dma_ctrl2_Reg</data>
+      <data key="MV">xilinx.com:ip:xdma:4.1</data>
+      <data key="TM">both</data>
+      <data key="SX">/</data>
+      <data key="SI">axil_dma_ctrl2</data>
+      <data key="SS">Reg</data>
+      <data key="SV">::design_1_imp:</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n19">
+      <data key="VM">design_1</data>
+      <data key="VT">BC</data>
+    </node>
+    <node id="n20">
       <data key="BA">0x00000000</data>
       <data key="BP">C_BASEADDR</data>
       <data key="HA">0x00007FFF</data>
@@ -298,14 +374,28 @@
       <data key="TU">memory</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n16">
-      <data key="VM">design_1</data>
-      <data key="VT">BC</data>
+    <node id="n21">
+      <data key="BA">0x0000000000</data>
+      <data key="BP">axibar_0</data>
+      <data key="HA">0xFFFFFFFFFF</data>
+      <data key="HP">axibar_highaddr_0</data>
+      <data key="MA">pcie_m_axi0</data>
+      <data key="MX">/</data>
+      <data key="MI">pcie_m_axi0</data>
+      <data key="MS">SEG_xdma_0_BAR0</data>
+      <data key="MV">:::</data>
+      <data key="TM">both</data>
+      <data key="SX">/xdma_0</data>
+      <data key="SI">S_AXI_B</data>
+      <data key="SS">BAR0</data>
+      <data key="SV">xilinx.com:ip:xdma:4.1</data>
+      <data key="TU">memory</data>
+      <data key="VT">AC</data>
     </node>
-    <node id="n17">
-      <data key="BA">0x80120000</data>
+    <node id="n22">
+      <data key="BA">0x80030000</data>
       <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x8012FFFF</data>
+      <data key="HA">0x8003FFFF</data>
       <data key="HP">C_HIGHADDR</data>
       <data key="MA">Data</data>
       <data key="MX">/microblaze_0</data>
@@ -320,17 +410,17 @@
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n18">
-      <data key="BA">0x83000000</data>
+    <node id="n23">
+      <data key="BA">0x0083000000</data>
       <data key="BP">baseaddr</data>
-      <data key="HA">0x83FFFFFF</data>
+      <data key="HA">0x0083FFFFFF</data>
       <data key="HP">highaddr</data>
-      <data key="MA">Data</data>
-      <data key="MX">/microblaze_0</data>
-      <data key="MI">M_AXI_DP</data>
+      <data key="MA">M_AXI_B</data>
+      <data key="MX">/xdma_0</data>
+      <data key="MI">M_AXI_B</data>
       <data key="MS">SEG_xdma_0_CTL0</data>
-      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
-      <data key="TM">data</data>
+      <data key="MV">xilinx.com:ip:xdma:4.1</data>
+      <data key="TM">both</data>
       <data key="SX">/xdma_0</data>
       <data key="SI">S_AXI_LITE</data>
       <data key="SS">CTL0</data>
@@ -338,25 +428,48 @@
       <data key="TU">memory</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n19">
-      <data key="BA">0x40000000</data>
+    <node id="n24">
+      <data key="BA">0x80130000</data>
       <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x4000FFFF</data>
+      <data key="HA">0x8013FFFF</data>
       <data key="HP">C_HIGHADDR</data>
       <data key="MA">Data</data>
       <data key="MX">/microblaze_0</data>
       <data key="MI">M_AXI_DP</data>
-      <data key="MS">SEG_axi_timer_0_Reg</data>
+      <data key="MS">SEG_axil_dma_ctrl3_Reg</data>
       <data key="MV">xilinx.com:ip:microblaze:11.0</data>
       <data key="TM">data</data>
-      <data key="SX">/axi_timer_0</data>
-      <data key="SI">S_AXI</data>
+      <data key="SX">/</data>
+      <data key="SI">axil_dma_ctrl3</data>
       <data key="SS">Reg</data>
-      <data key="SV">xilinx.com:ip:axi_timer:2.0</data>
+      <data key="SV">::design_1_imp:</data>
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n20">
+    <node id="n25">
+      <data key="VH">2</data>
+      <data key="VM">design_1</data>
+      <data key="VT">VR</data>
+    </node>
+    <node id="n26">
+      <data key="BA">0x80020000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0x8002FFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">Data</data>
+      <data key="MX">/microblaze_0</data>
+      <data key="MI">M_AXI_DP</data>
+      <data key="MS">SEG_axil_timing_Reg</data>
+      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
+      <data key="TM">data</data>
+      <data key="SX">/</data>
+      <data key="SI">axil_timing</data>
+      <data key="SS">Reg</data>
+      <data key="SV">::design_1_imp:</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n27">
       <data key="BA">0x00000000</data>
       <data key="BP">C_BASEADDR</data>
       <data key="HA">0x00007FFF</data>
@@ -374,131 +487,144 @@
       <data key="TU">memory</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n21">
-      <data key="TU">active</data>
-      <data key="VH">2</data>
-      <data key="VT">PM</data>
+    <node id="n28">
+      <data key="BA">0x83000000</data>
+      <data key="BP">baseaddr</data>
+      <data key="HA">0x83FFFFFF</data>
+      <data key="HP">highaddr</data>
+      <data key="MA">Data</data>
+      <data key="MX">/microblaze_0</data>
+      <data key="MI">M_AXI_DP</data>
+      <data key="MS">SEG_xdma_0_CTL0</data>
+      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
+      <data key="TM">data</data>
+      <data key="SX">/xdma_0</data>
+      <data key="SI">S_AXI_LITE</data>
+      <data key="SS">CTL0</data>
+      <data key="SV">xilinx.com:ip:xdma:4.1</data>
+      <data key="TU">memory</data>
+      <data key="VT">AC</data>
     </node>
-    <node id="n22">
-      <data key="BA">0x0080120000</data>
+    <node id="n29">
+      <data key="BA">0x80120000</data>
       <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x008012FFFF</data>
+      <data key="HA">0x8012FFFF</data>
       <data key="HP">C_HIGHADDR</data>
-      <data key="MA">M_AXI_B</data>
-      <data key="MX">/xdma_0</data>
-      <data key="MI">M_AXI_B</data>
-      <data key="MS">SEG_axil_data_gen_Reg</data>
-      <data key="MV">xilinx.com:ip:xdma:4.1</data>
-      <data key="TM">both</data>
+      <data key="MA">Data</data>
+      <data key="MX">/microblaze_0</data>
+      <data key="MI">M_AXI_DP</data>
+      <data key="MS">SEG_axil_dma_ctrl2_Reg</data>
+      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
+      <data key="TM">data</data>
       <data key="SX">/</data>
-      <data key="SI">axil_data_gen</data>
+      <data key="SI">axil_dma_ctrl2</data>
       <data key="SS">Reg</data>
       <data key="SV">::design_1_imp:</data>
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n23">
-      <data key="BA">0x80000000</data>
+    <node id="n30">
+      <data key="BA">0x80100000</data>
       <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x8000FFFF</data>
+      <data key="HA">0x8010FFFF</data>
       <data key="HP">C_HIGHADDR</data>
       <data key="MA">Data</data>
       <data key="MX">/microblaze_0</data>
       <data key="MI">M_AXI_DP</data>
-      <data key="MS">SEG_axil_descriptors_Reg</data>
+      <data key="MS">SEG_axil_dma_ctrl0_Reg</data>
       <data key="MV">xilinx.com:ip:microblaze:11.0</data>
       <data key="TM">data</data>
       <data key="SX">/</data>
-      <data key="SI">axil_descriptors</data>
+      <data key="SI">axil_dma_ctrl0</data>
       <data key="SS">Reg</data>
       <data key="SV">::design_1_imp:</data>
       <data key="TU">register</data>
       <data key="VT">AC</data>
     </node>
-    <node id="n24">
-      <data key="BA">0x40010000</data>
-      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0x4001FFFF</data>
-      <data key="HP">C_HIGHADDR</data>
-      <data key="MA">Data</data>
-      <data key="MX">/microblaze_0</data>
-      <data key="MI">M_AXI_DP</data>
-      <data key="MS">SEG_axi_uartlite_0_Reg</data>
-      <data key="MV">xilinx.com:ip:microblaze:11.0</data>
-      <data key="TM">data</data>
-      <data key="SX">/axi_uartlite_0</data>
-      <data key="SI">S_AXI</data>
-      <data key="SS">Reg</data>
-      <data key="SV">xilinx.com:ip:axi_uartlite:2.0</data>
-      <data key="TU">register</data>
-      <data key="VT">AC</data>
-    </node>
-    <edge id="e0" source="n16" target="n11"/>
-    <edge id="e1" source="n11" target="n21"/>
-    <edge id="e2" source="n7" target="n21">
+    <edge id="e0" source="n19" target="n25"/>
+    <edge id="e1" source="n25" target="n6"/>
+    <edge id="e2" source="n2" target="n6">
       <data key="EH">2</data>
     </edge>
-    <edge id="e3" source="n3" target="n21">
+    <edge id="e3" source="n3" target="n6">
       <data key="EH">2</data>
     </edge>
-    <edge id="e4" source="n19" target="n21">
+    <edge id="e4" source="n27" target="n6">
       <data key="EH">2</data>
     </edge>
-    <edge id="e5" source="n24" target="n21">
+    <edge id="e5" source="n9" target="n6">
       <data key="EH">2</data>
     </edge>
-    <edge id="e6" source="n17" target="n21">
+    <edge id="e6" source="n17" target="n6">
       <data key="EH">2</data>
     </edge>
-    <edge id="e7" source="n23" target="n21">
+    <edge id="e7" source="n28" target="n6">
       <data key="EH">2</data>
     </edge>
-    <edge id="e8" source="n12" target="n21">
+    <edge id="e8" source="n20" target="n6">
       <data key="EH">2</data>
     </edge>
-    <edge id="e9" source="n1" target="n21">
+    <edge id="e9" source="n4" target="n6">
       <data key="EH">2</data>
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project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0.xci

@@ -24,7 +24,7 @@
         "Component_Name": [ { "value": "design_1_auto_cc_0", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -43,11 +43,11 @@
         "C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0.xci

@@ -12,7 +12,7 @@
         "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
         "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "PACKING_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "SI_DATA_WIDTH": [ { "value": "256", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SI_DATA_WIDTH": [ { "value": "512", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "MI_DATA_WIDTH": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "SI_ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "MAX_SPLIT_BEATS": [ { "value": "256", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -23,12 +23,12 @@
         "Component_Name": [ { "value": "design_1_auto_ds_0", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_SUPPORTS_ID": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_S_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -41,11 +41,11 @@
         "C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -82,8 +82,8 @@
         "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
         "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
         "s_axi_awready": [ { "direction": "out" } ],
-        "s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
-        "s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0xFFFFFFFFFFFFFFFF" } ],
         "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
         "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
         "s_axi_wready": [ { "direction": "out" } ],
@@ -104,7 +104,7 @@
         "s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
         "s_axi_arready": [ { "direction": "out" } ],
         "s_axi_rid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
-        "s_axi_rdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
         "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
         "s_axi_rlast": [ { "direction": "out" } ],
         "s_axi_rvalid": [ { "direction": "out" } ],
@@ -151,7 +151,7 @@
           "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
           "mode": "slave",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "ID_WIDTH": [ { "value": "4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -173,7 +173,7 @@
             "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -252,7 +252,7 @@
             "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.xci

@@ -23,7 +23,7 @@
         "Component_Name": [ { "value": "design_1_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_IGNORE_ID": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -41,11 +41,11 @@
         "C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -153,7 +153,7 @@
             "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -228,7 +228,7 @@
             "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0/design_1_auto_us_0.xci

@@ -0,0 +1,265 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "design_1_auto_us_0",
+    "cell_name": "axi_interconnect_1/s00_couplers/auto_us",
+    "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1",
+    "ip_revision": "27",
+    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_us_0",
+    "parameters": {
+      "component_parameters": {
+        "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PACKING_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SI_DATA_WIDTH": [ { "value": "256", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MI_DATA_WIDTH": [ { "value": "512", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SI_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MAX_SPLIT_BEATS": [ { "value": "256", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "FIFO_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+        "C_MAX_SPLIT_BEATS": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
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+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
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+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
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+        "IPREVISION": [ { "value": "27" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_us_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
+        "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
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+        "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "s_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ]
+          }
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+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "m_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "m_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "m_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "m_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "m_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready" } ]
+          }
+        },
+        "SI_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "SI_RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_1/design_1_auto_us_1.xci

@@ -0,0 +1,265 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "design_1_auto_us_1",
+    "cell_name": "axi_interconnect_1/s01_couplers/auto_us",
+    "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1",
+    "ip_revision": "27",
+    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_us_1",
+    "parameters": {
+      "component_parameters": {
+        "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PACKING_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SI_DATA_WIDTH": [ { "value": "256", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MI_DATA_WIDTH": [ { "value": "512", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SI_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MAX_SPLIT_BEATS": [ { "value": "256", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "FIFO_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ACLK_ASYNC": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ACLK_RATIO": [ { "value": "1:2", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "design_1_auto_us_1", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SUPPORTS_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_READ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FIFO_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ACLK_RATIO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_ACLK_RATIO": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MAX_SPLIT_BEATS": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PACKING_LEVEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "27" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_us_1" } ],
+        "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
+        "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
+        "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
+        "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ],
+        "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
+        "m_axi_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awvalid": [ { "direction": "out" } ],
+        "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "m_axi_wlast": [ { "direction": "out" } ],
+        "m_axi_wvalid": [ { "direction": "out" } ],
+        "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bready": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "s_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ]
+          }
+        },
+        "M_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "m_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "m_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "m_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "m_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "m_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready" } ]
+          }
+        },
+        "SI_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "SI_RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_2/design_1_auto_us_2.xci

@@ -0,0 +1,265 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "design_1_auto_us_2",
+    "cell_name": "axi_interconnect_1/s02_couplers/auto_us",
+    "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1",
+    "ip_revision": "27",
+    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_us_2",
+    "parameters": {
+      "component_parameters": {
+        "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PACKING_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SI_DATA_WIDTH": [ { "value": "256", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MI_DATA_WIDTH": [ { "value": "512", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SI_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MAX_SPLIT_BEATS": [ { "value": "256", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "FIFO_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ACLK_ASYNC": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ACLK_RATIO": [ { "value": "1:2", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "design_1_auto_us_2", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SUPPORTS_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_READ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FIFO_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ACLK_RATIO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_ACLK_RATIO": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MAX_SPLIT_BEATS": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PACKING_LEVEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "27" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_us_2" } ],
+        "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
+        "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
+        "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
+        "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ],
+        "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
+        "m_axi_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awvalid": [ { "direction": "out" } ],
+        "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "m_axi_wlast": [ { "direction": "out" } ],
+        "m_axi_wvalid": [ { "direction": "out" } ],
+        "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bready": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "s_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ]
+          }
+        },
+        "M_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "m_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "m_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "m_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "m_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "m_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready" } ]
+          }
+        },
+        "SI_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "SI_RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_3/design_1_auto_us_3.xci

@@ -0,0 +1,265 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "design_1_auto_us_3",
+    "cell_name": "axi_interconnect_1/s03_couplers/auto_us",
+    "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1",
+    "ip_revision": "27",
+    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_us_3",
+    "parameters": {
+      "component_parameters": {
+        "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
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+        "SI_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+        "Component_Name": [ { "value": "design_1_auto_us_3", "resolve_type": "user", "usage": "all" } ]
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+        "C_M_AXI_ACLK_RATIO": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_MAX_SPLIT_BEATS": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
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+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
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+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
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+        "IPREVISION": [ { "value": "27" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_us_3" } ],
+        "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
+        "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
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+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
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+        "m_axi_awregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
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+        "m_axi_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
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+        "m_axi_wvalid": [ { "direction": "out" } ],
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+        "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bready": [ { "direction": "out" } ]
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "s_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ]
+          }
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+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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+            "HAS_QOS": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "m_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "m_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "m_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "m_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "m_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready" } ]
+          }
+        },
+        "SI_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "SI_RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_0_0/design_1_axi_interconnect_0_0.xci

@@ -325,11 +325,11 @@
         "Component_Name": [ { "value": "design_1_axi_interconnect_0_0", "resolve_type": "user", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_1_0/design_1_axi_interconnect_1_0.xci

@@ -8,7 +8,7 @@
     "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_axi_interconnect_1_0",
     "parameters": {
       "component_parameters": {
-        "NUM_SI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_SI": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -164,8 +164,8 @@
         "S15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S00_HAS_DATA_FIFO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S01_HAS_DATA_FIFO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "S02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "S03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S02_HAS_DATA_FIFO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S03_HAS_DATA_FIFO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -325,11 +325,11 @@
         "Component_Name": [ { "value": "design_1_axi_interconnect_1_0", "resolve_type": "user", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci

@@ -18,7 +18,7 @@
         "enable_timer2": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_COUNT_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ONE_TIMER_ONLY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_TRIG0_ASSERT": [ { "value": "1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
@@ -29,11 +29,11 @@
         "C_S_AXI_ADDR_WIDTH": [ { "value": "5", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0.xci

@@ -1,364 +0,0 @@
-{
-  "schema": "xilinx.com:schema:json_instance:1.0",
-  "ip_inst": {
-    "xci_name": "design_1_axi_uartlite_0_0",
-    "cell_name": "axi_uartlite_0",
-    "component_reference": "xilinx.com:ip:axi_uartlite:2.0",
-    "ip_revision": "31",
-    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0",
-    "parameters": {
-      "component_parameters": {
-        "C_DATA_BITS": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_BAUDRATE": [ { "value": "115200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_S_AXI_ACLK_FREQ_HZ_d": [ { "value": "100.0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "Component_Name": [ { "value": "design_1_axi_uartlite_0_0", "resolve_type": "user", "usage": "all" } ],
-        "PARITY": [ { "value": "No_Parity", "resolve_type": "user", "usage": "all" } ],
-        "C_USE_PARITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_ODD_PARITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "UARTLITE_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
-      },
-      "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
-        "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_S_AXI_ADDR_WIDTH": [ { "value": "4", "format": "long", "usage": "all" } ],
-        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
-        "C_BAUDRATE": [ { "value": "115200", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_DATA_BITS": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_USE_PARITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_ODD_PARITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
-      },
-      "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
-        "BASE_BOARD_PART": [ { "value": "" } ],
-        "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
-        "SILICON_REVISION": [ { "value": "" } ],
-        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
-        "SPEEDGRADE": [ { "value": "-2" } ],
-        "STATIC_POWER": [ { "value": "" } ],
-        "TEMPERATURE_GRADE": [ { "value": "I" } ],
-        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
-        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
-      },
-      "runtime_parameters": {
-        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
-        "IPREVISION": [ { "value": "31" } ],
-        "MANAGED": [ { "value": "TRUE" } ],
-        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0" } ],
-        "SELECTEDSIMMODEL": [ { "value": "" } ],
-        "SHAREDDIR": [ { "value": "../../ipshared" } ],
-        "SWVERSION": [ { "value": "2022.2" } ],
-        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
-      }
-    },
-    "boundary": {
-      "ports": {
-        "s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
-        "s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ],
-        "interrupt": [ { "direction": "out" } ],
-        "s_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
-        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
-        "s_axi_awready": [ { "direction": "out" } ],
-        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
-        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
-        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
-        "s_axi_wready": [ { "direction": "out" } ],
-        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
-        "s_axi_bvalid": [ { "direction": "out" } ],
-        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
-        "s_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
-        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
-        "s_axi_arready": [ { "direction": "out" } ],
-        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
-        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
-        "s_axi_rvalid": [ { "direction": "out" } ],
-        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
-        "rx": [ { "direction": "in", "driver_value": "0" } ],
-        "tx": [ { "direction": "out" } ]
-      },
-      "interfaces": {
-        "S_AXI": {
-          "vlnv": "xilinx.com:interface:aximm:1.0",
-          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
-          "mode": "slave",
-          "parameters": {
-            "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ADDR_WIDTH": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
-            "CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
-          },
-          "port_maps": {
-            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
-            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
-            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
-            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
-            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
-            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
-            "BREADY": [ { "physical_name": "s_axi_bready" } ],
-            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
-            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
-            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
-            "RREADY": [ { "physical_name": "s_axi_rready" } ],
-            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
-            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
-            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
-            "WREADY": [ { "physical_name": "s_axi_wready" } ],
-            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
-            "WVALID": [ { "physical_name": "s_axi_wvalid" } ]
-          }
-        },
-        "ACLK": {
-          "vlnv": "xilinx.com:signal:clock:1.0",
-          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
-          "mode": "slave",
-          "parameters": {
-            "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
-            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
-            "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
-            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
-            "CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
-          },
-          "port_maps": {
-            "CLK": [ { "physical_name": "s_axi_aclk" } ]
-          }
-        },
-        "ARESETN": {
-          "vlnv": "xilinx.com:signal:reset:1.0",
-          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
-          "mode": "slave",
-          "parameters": {
-            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
-            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
-          },
-          "port_maps": {
-            "RST": [ { "physical_name": "s_axi_aresetn" } ]
-          }
-        },
-        "INTERRUPT": {
-          "vlnv": "xilinx.com:signal:interrupt:1.0",
-          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
-          "mode": "master",
-          "parameters": {
-            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
-            "PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
-          },
-          "port_maps": {
-            "INTERRUPT": [ { "physical_name": "interrupt" } ]
-          }
-        },
-        "UART": {
-          "vlnv": "xilinx.com:interface:uart:1.0",
-          "abstraction_type": "xilinx.com:interface:uart_rtl:1.0",
-          "mode": "master",
-          "parameters": {
-            "BOARD.ASSOCIATED_PARAM": [ { "value": "UARTLITE_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
-          },
-          "port_maps": {
-            "RxD": [ { "physical_name": "rx" } ],
-            "TxD": [ { "physical_name": "tx" } ]
-          }
-        }
-      },
-      "memory_maps": {
-        "S_AXI": {
-          "display_name": "S_AXI_MEM",
-          "description": "Memory Map for S_AXI",
-          "address_blocks": {
-            "Reg": {
-              "base_address": "0",
-              "range": "4096",
-              "display_name": "Reg",
-              "description": "Register Block",
-              "usage": "register",
-              "access": "read-write",
-              "registers": {
-                "RX_FIFO": {
-                  "address_offset": "0x0",
-                  "size": 32,
-                  "display_name": "RX FIFO",
-                  "description": "Receive data FIFO",
-                  "is_volatile": true,
-                  "access": "read-only",
-                  "reset_value": "0x0",
-                  "fields": {
-                    "RX_DATA": {
-                      "bit_offset": 0,
-                      "bit_width": 8,
-                      "display_name": "Receive Data",
-                      "description": "UART Receive Data\n",
-                      "is_volatile": true,
-                      "access": "read-only"
-                    }
-                  }
-                },
-                "TX_FIFO": {
-                  "address_offset": "0x4",
-                  "size": 32,
-                  "display_name": "TX FIFO",
-                  "description": "Transmit data FIFO",
-                  "is_volatile": true,
-                  "access": "write-only",
-                  "reset_value": "0x0",
-                  "fields": {
-                    "TX_DATA": {
-                      "bit_offset": 0,
-                      "bit_width": 8,
-                      "display_name": "Transmit Data",
-                      "description": "UART Transmit Data\n",
-                      "is_volatile": true,
-                      "access": "write-only"
-                    }
-                  }
-                },
-                "CTRL_REG": {
-                  "address_offset": "0xC",
-                  "size": 32,
-                  "display_name": "Control Register",
-                  "description": "UART Lite control register",
-                  "is_volatile": true,
-                  "access": "write-only",
-                  "reset_value": "0x0",
-                  "fields": {
-                    "RST_TXFIFO": {
-                      "bit_offset": 0,
-                      "bit_width": 1,
-                      "display_name": "Reset Tx FIFO",
-                      "description": "Reset/clear the transmit FIFO\nWriting a 1 to this bit position clears the transmit FIFO\n  0 - Do nothing\n  1 - Clear the transmit FIFO\n",
-                      "is_volatile": true,
-                      "access": "write-only"
-                    },
-                    "RST_RXFIFO": {
-                      "bit_offset": 1,
-                      "bit_width": 1,
-                      "display_name": "Reset Rx FIFO",
-                      "description": "Reset/clear the receive FIFO\nWriting a 1 to this bit position clears the receive FIFO\n  0 - Do nothing\n  1 - Clear the receive FIFO\n",
-                      "is_volatile": true,
-                      "access": "write-only"
-                    },
-                    "Enable_Intr": {
-                      "bit_offset": 4,
-                      "bit_width": 1,
-                      "display_name": "Enable interrupt",
-                      "description": "Enable interrupt for the AXI UART Lite\n  0 - Disable interrupt signal\n  1 - Enable interrupt signal\n",
-                      "is_volatile": true,
-                      "access": "write-only"
-                    }
-                  }
-                },
-                "STAT_REG": {
-                  "address_offset": "0x8",
-                  "size": 32,
-                  "display_name": "Status Register",
-                  "description": "UART Lite status register",
-                  "is_volatile": true,
-                  "access": "read-only",
-                  "reset_value": "0x0",
-                  "fields": {
-                    "RX_FIFO_Valid_Data": {
-                      "bit_offset": 0,
-                      "bit_width": 1,
-                      "display_name": "RX FIFO Valid Data",
-                      "description": "Indicates if the receive FIFO has data.\n  0 - Receive FIFO is empty\n  1 - Receive FIFO has data\n",
-                      "is_volatile": true,
-                      "access": "read-only"
-                    },
-                    "RX_FIFO_Full": {
-                      "bit_offset": 1,
-                      "bit_width": 1,
-                      "display_name": "RX FIFO Full",
-                      "description": "Indicates if the receive FIFO is full.\n  0 - Receive FIFO is not full\n  1 - Receive FIFO is full\n",
-                      "is_volatile": true,
-                      "access": "read-only"
-                    },
-                    "TX_FIFO_Empty": {
-                      "bit_offset": 2,
-                      "bit_width": 1,
-                      "display_name": "TX FIFO Empty",
-                      "description": "Indicates if the transmit FIFO is empty.\n  0 - Transmit FIFO is not empty\n  1 - Transmit FIFO is empty\n",
-                      "is_volatile": true,
-                      "access": "read-only"
-                    },
-                    "TX_FIFO_Full": {
-                      "bit_offset": 3,
-                      "bit_width": 1,
-                      "display_name": "TX FIFO Full",
-                      "description": "Indicates if the transmit FIFO is full.\n  0 - Transmit FIFO is not full\n  1 - Transmit FIFO is full\n",
-                      "is_volatile": true,
-                      "access": "read-only"
-                    },
-                    "Intr_Enabled": {
-                      "bit_offset": 4,
-                      "bit_width": 1,
-                      "display_name": "Interrupt Enabled",
-                      "description": "Indicates that interrupts is enabled.\n  0 - Interrupt is disabled\n  1 - Interrupt is enabled\n",
-                      "is_volatile": true,
-                      "access": "read-only"
-                    },
-                    "Overrun_Error": {
-                      "bit_offset": 5,
-                      "bit_width": 1,
-                      "display_name": "Overrun Error",
-                      "description": "Indicates that a overrun error has occurred after the last time the status register was read. Overrun is when a new character has been received but the receive FIFO is full. The received character is ignored and not written into the receive FIFO. This bit is cleared when the status register is read.      0 - No overrun error has occurred      1 - Overrun error has occurred\n",
-                      "is_volatile": true,
-                      "access": "read-only"
-                    },
-                    "Frame_Error": {
-                      "bit_offset": 6,
-                      "bit_width": 1,
-                      "display_name": "Frame Error",
-                      "description": "Indicates that a frame error has occurred after the last time the status register was read. Frame error is defined as detection of a stop bit with the value 0. The receive character is ignored and not written to the receive FIFO. This bit is cleared when the status register is read.      0 - No frame error has occurred   1 - Frame error has occurred\n",
-                      "is_volatile": true,
-                      "access": "read-only"
-                    },
-                    "Parity_Error": {
-                      "bit_offset": 7,
-                      "bit_width": 1,
-                      "display_name": "Parity Error",
-                      "description": "Indicates that a parity error has occurred after the last time the status register was read. If the UART is configured without any parity handling, this bit is always 0. The received character is written into the receive FIFO. This bit is cleared when the status register is read.      0 - No parity error has occurred      1 - Parity error has occurred\n",
-                      "is_volatile": true,
-                      "access": "read-only"
-                    }
-                  }
-                }
-              }
-            }
-          }
-        }
-      }
-    }
-  }
-}

project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xci

@@ -33,7 +33,7 @@
         "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
-        "PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_FREQ": [ { "value": "100", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
         "PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "user", "usage": "all" } ],
@@ -49,7 +49,7 @@
         "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN1_JITTER_PS": [ { "value": "100.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -157,11 +157,11 @@
         "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
         "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
-        "MMCM_CLKFBOUT_MULT_F": [ { "value": "6.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
@@ -246,8 +246,8 @@
         "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
         "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_JITTER": [ { "value": "106.024", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "CLKOUT1_PHASE_ERROR": [ { "value": "82.655", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_JITTER": [ { "value": "115.831", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_PHASE_ERROR": [ { "value": "87.180", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -308,7 +308,7 @@
         "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
         "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_PRIM_IN_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIM_IN_FREQ": [ { "value": "100", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
         "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
@@ -335,11 +335,11 @@
         "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
         "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
         "C_INCLK_SUM_ROW0": [ { "value": "Input Clock   Freq (MHz)    Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
-        "C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW1": [ { "value": "__primary_____________100____________0.010", "resolve_type": "generated", "usage": "all" } ],
         "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
-        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__100.00000______0.000______50.0______106.024_____82.655", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__100.00000______0.000______50.0______115.831_____87.180", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
         "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
@@ -399,9 +399,9 @@
         "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
         "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
-        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "6.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
-        "C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
-        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
         "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
         "C_MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
@@ -503,7 +503,7 @@
         "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
         "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
         "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
-        "C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
         "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
@@ -584,11 +584,11 @@
         "C_VCO_MAX": [ { "value": "1600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -624,7 +624,7 @@
           "parameters": {
             "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
             "CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
-            "FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
             "CLK_N": [ { "physical_name": "clk_in1_n" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci

@@ -35,7 +35,7 @@
         "Component_Name": [ { "value": "design_1_dlmb_bram_if_cntlr_0", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_HIGHADDR": [ { "value": "0x0000000000007FFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_BASEADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_NUM_LMB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -61,11 +61,11 @@
         "C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci

@@ -23,11 +23,11 @@
         "C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci

@@ -35,7 +35,7 @@
         "Component_Name": [ { "value": "design_1_ilmb_bram_if_cntlr_0", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_HIGHADDR": [ { "value": "0x0000000000007FFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_BASEADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_NUM_LMB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -61,11 +61,11 @@
         "C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci

@@ -23,11 +23,11 @@
         "C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci

@@ -82,8 +82,8 @@
         "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
-        "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
         "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -159,11 +159,11 @@
         "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     17.246228 mW", "resolve_type": "generated", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xci

@@ -19,17 +19,17 @@
         "C_INTERCONNECT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_S_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_M_AXI_ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_ADDR_WIDTH": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_M_AXI_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_ADDR_SIZE": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ADDR_SIZE": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_DATA_SIZE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_LMB_PROTOCOL": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_M_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_M_AXIS_ID_WIDTH": [ { "value": "7", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_MB_DBG_PORTS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_USE_UART": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_UART": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_DBG_REG_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_DBG_MEM_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_USE_CROSS_TRIGGER": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -46,8 +46,8 @@
         "Component_Name": [ { "value": "design_1_mdm_1_0", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
-        "C_DEVICE": [ { "value": "xczu7ev", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEVICE": [ { "value": "xcku15p", "resolve_type": "generated", "usage": "all" } ],
         "C_REVISION": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
         "C_JTAG_CHAIN": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_USE_BSCAN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -55,9 +55,9 @@
         "C_DEBUG_INTERFACE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_USE_CONFIG_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AVOID_PRIMITIVES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_INTERCONNECT": [ { "value": "2", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_INTERCONNECT": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_MB_DBG_PORTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_USE_UART": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_UART": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_DBG_REG_ACCESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_DBG_MEM_ACCESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_USE_CROSS_TRIGGER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -69,9 +69,9 @@
         "C_TRACE_ASYNC_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
         "C_TRACE_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
         "C_TRACE_ID": [ { "value": "110", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
-        "C_S_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
-        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
-        "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_M_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
         "C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
         "C_M_AXI_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
@@ -82,11 +82,11 @@
         "C_M_AXIS_ID_WIDTH": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -109,7 +109,27 @@
     },
     "boundary": {
       "ports": {
+        "S_AXI_ACLK": [ { "direction": "in", "driver_value": "0" } ],
+        "S_AXI_ARESETN": [ { "direction": "in", "driver_value": "0" } ],
+        "Interrupt": [ { "direction": "out" } ],
         "Debug_SYS_Rst": [ { "direction": "out" } ],
+        "S_AXI_AWADDR": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S_AXI_AWVALID": [ { "direction": "in", "driver_value": "0" } ],
+        "S_AXI_AWREADY": [ { "direction": "out" } ],
+        "S_AXI_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "S_AXI_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S_AXI_WVALID": [ { "direction": "in", "driver_value": "0" } ],
+        "S_AXI_WREADY": [ { "direction": "out" } ],
+        "S_AXI_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "S_AXI_BVALID": [ { "direction": "out" } ],
+        "S_AXI_BREADY": [ { "direction": "in", "driver_value": "0" } ],
+        "S_AXI_ARADDR": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "S_AXI_ARVALID": [ { "direction": "in", "driver_value": "0" } ],
+        "S_AXI_ARREADY": [ { "direction": "out" } ],
+        "S_AXI_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "S_AXI_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "S_AXI_RVALID": [ { "direction": "out" } ],
+        "S_AXI_RREADY": [ { "direction": "in", "driver_value": "0" } ],
         "Dbg_Clk_0": [ { "direction": "out" } ],
         "Dbg_TDI_0": [ { "direction": "out" } ],
         "Dbg_TDO_0": [ { "direction": "in", "driver_value": "0" } ],
@@ -121,6 +141,94 @@
         "Dbg_Disable_0": [ { "direction": "out" } ]
       },
       "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S_AXI",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ARADDR": [ { "physical_name": "S_AXI_ARADDR" } ],
+            "ARREADY": [ { "physical_name": "S_AXI_ARREADY" } ],
+            "ARVALID": [ { "physical_name": "S_AXI_ARVALID" } ],
+            "AWADDR": [ { "physical_name": "S_AXI_AWADDR" } ],
+            "AWREADY": [ { "physical_name": "S_AXI_AWREADY" } ],
+            "AWVALID": [ { "physical_name": "S_AXI_AWVALID" } ],
+            "BREADY": [ { "physical_name": "S_AXI_BREADY" } ],
+            "BRESP": [ { "physical_name": "S_AXI_BRESP" } ],
+            "BVALID": [ { "physical_name": "S_AXI_BVALID" } ],
+            "RDATA": [ { "physical_name": "S_AXI_RDATA" } ],
+            "RREADY": [ { "physical_name": "S_AXI_RREADY" } ],
+            "RRESP": [ { "physical_name": "S_AXI_RRESP" } ],
+            "RVALID": [ { "physical_name": "S_AXI_RVALID" } ],
+            "WDATA": [ { "physical_name": "S_AXI_WDATA" } ],
+            "WREADY": [ { "physical_name": "S_AXI_WREADY" } ],
+            "WSTRB": [ { "physical_name": "S_AXI_WSTRB" } ],
+            "WVALID": [ { "physical_name": "S_AXI_WVALID" } ]
+          }
+        },
+        "CLK.S_AXI_ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:MBDEBUG_AXI_0:MBDEBUG_AXI_1:MBDEBUG_AXI_2:MBDEBUG_AXI_3:MBDEBUG_AXI_4:MBDEBUG_AXI_5:MBDEBUG_AXI_6:MBDEBUG_AXI_7:MBDEBUG_AXI_8:MBDEBUG_AXI_9:MBDEBUG_AXI_10:MBDEBUG_AXI_11:MBDEBUG_AXI_12:MBDEBUG_AXI_13:MBDEBUG_AXI_14:MBDEBUG_AXI_15:MBDEBUG_AXI_16:MBDEBUG_AXI_17:MBDEBUG_AXI_18:MBDEBUG_AXI_19:MBDEBUG_AXI_20:MBDEBUG_AXI_21:MBDEBUG_AXI_22:MBDEBUG_AXI_23:MBDEBUG_AXI_24:MBDEBUG_AXI_25:MBDEBUG_AXI_26:MBDEBUG_AXI_27:MBDEBUG_AXI_28:MBDEBUG_AXI_29:MBDEBUG_AXI_30:MBDEBUG_AXI_31", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "S_AXI_ACLK" } ]
+          }
+        },
+        "RST.S_AXI_ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "S_AXI_ARESETN" } ]
+          }
+        },
         "RST.Debug_SYS_Rst": {
           "vlnv": "xilinx.com:signal:reset:1.0",
           "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
@@ -148,6 +256,19 @@
             "TDO": [ { "physical_name": "Dbg_TDO_0" } ],
             "UPDATE": [ { "physical_name": "Dbg_Update_0" } ]
           }
+        },
+        "INTERRUPT.INTERRUPT": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "SUGGESTED_PRIORITY": [ { "value": "HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "INTERRUPT": [ { "physical_name": "Interrupt" } ]
+          }
         }
       },
       "memory_maps": {
@@ -160,7 +281,141 @@
               "display_name": "Reg",
               "description": "Register Block",
               "usage": "register",
-              "access": "read-write"
+              "access": "read-write",
+              "registers": {
+                "UART_Receive": {
+                  "address_offset": "0x0",
+                  "size": 8,
+                  "display_name": "JTAG UART Receive Data",
+                  "description": "JTAG UART Receive Data",
+                  "is_volatile": true,
+                  "access": "read-only",
+                  "reset_value": "0",
+                  "fields": {
+                    "UART_RX": {
+                      "bit_offset": 0,
+                      "bit_width": 8,
+                      "display_name": "UART_RX",
+                      "description": "UART Receive Data.",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    }
+                  }
+                },
+                "UART_Transmit": {
+                  "address_offset": "0x4",
+                  "size": 8,
+                  "display_name": "JTAG UART Transmit Data",
+                  "description": "JTAG UART Transmit Data",
+                  "is_volatile": true,
+                  "access": "write-only",
+                  "reset_value": "0",
+                  "fields": {
+                    "UART_TX": {
+                      "bit_offset": 0,
+                      "bit_width": 8,
+                      "display_name": "UART_TX",
+                      "description": "UART Transmit Data.",
+                      "is_volatile": true,
+                      "access": "write-only"
+                    }
+                  }
+                },
+                "UART_Status": {
+                  "address_offset": "0x8",
+                  "size": 5,
+                  "display_name": "JTAG UART Status Register",
+                  "description": "JTAG UART Status Register",
+                  "is_volatile": true,
+                  "access": "read-only",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "RX_FIFO_Valid_Data": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "RX FIFO Valid Data",
+                      "description": "Indicates if the receive FIFO has valid data:\n  0 - Receive FIFO is empty.\n  1 - Receive FIFO has valid data.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "RX_FIFO_Full": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "RX FIFO Full",
+                      "description": "Indicates if the receive FIFO is full:\n  0 - Receive FIFO is not full.\n  1 - Receive FIFO is full.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "TX_FIFO_Empty": {
+                      "bit_offset": 2,
+                      "bit_width": 1,
+                      "display_name": "TX FIFO Empty",
+                      "description": "Indicates if the transmit FIFO is empty:\n  0 - Transmit FIFO is not empty.\n  1 - Transmit FIFO is empty.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "TX_FIFO_Full": {
+                      "bit_offset": 3,
+                      "bit_width": 1,
+                      "display_name": "TX FIFO Full",
+                      "description": "Indicates if the transmit FIFO is full:\n  0 - Transmit FIFO is not full.\n  1 - Transmit FIFO is full.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    },
+                    "Interrupt_Enabled": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "Interrupt Enabled",
+                      "description": "Indicates that interrupt is enabled:\n  0 - Interrupt is disabled.\n  1 - Interrupt is enabled.\n",
+                      "is_volatile": true,
+                      "access": "read-only"
+                    }
+                  }
+                },
+                "UART_Control": {
+                  "address_offset": "0xC",
+                  "size": 5,
+                  "display_name": "JTAG UART Control Register",
+                  "description": "JTAG UART Control Register",
+                  "is_volatile": true,
+                  "access": "write-only",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Reset_TX_FIFO": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Reset TX FIFO",
+                      "description": "Reset/clear the transmit FIFO:\n  0 - Do nothing.\n  1 - Clear the transmit FIFO.\n",
+                      "is_volatile": true,
+                      "access": "write-only"
+                    },
+                    "Reset_RX_FIFO": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "Reset RX FIFO",
+                      "description": "Reset/clear the receive FIFO:\n  0 - Do nothing.\n  1 - Clear the receive FIFO.\n",
+                      "is_volatile": true,
+                      "access": "write-only"
+                    },
+                    "Clear_EXT_BRK": {
+                      "bit_offset": 2,
+                      "bit_width": 1,
+                      "display_name": "Clear EXT_BRK",
+                      "description": "Clear the EXT_BRK signal set by JTAG:\n  0 - Do nothing.\n  1 - Clear the signal.\n",
+                      "is_volatile": true,
+                      "access": "write-only"
+                    },
+                    "Interrupt_Enabled": {
+                      "bit_offset": 4,
+                      "bit_width": 1,
+                      "display_name": "Interrupt Enabled",
+                      "description": "Indicates interrupt for the MDM JTAG UART:\n  0 - Disable interrupt interrupt.\n  1 - Enable interrupt signal.\n",
+                      "is_volatile": true,
+                      "access": "write-only"
+                    }
+                  }
+                }
+              }
             }
           }
         }

project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xci

@@ -237,7 +237,7 @@
         "C_LOCKSTEP_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_TEMPORAL_DEPTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ENDIANNESS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_DATA_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_LMB_DATA_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_INSTR_SIZE": [ { "value": "32", "format": "long", "usage": "all" } ],
@@ -394,11 +394,11 @@
         "C_M_AXI_DC_BUSER_WIDTH": [ { "value": "1", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci

@@ -18,7 +18,7 @@
         "C_NUM_INTR_INPUTS": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_NUM_SW_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_KIND_OF_LVL": [ { "value": "0xFFFFFFFF", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "C_ASYNC_INTR": [ { "value": "0xFFFFFFF8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_ASYNC_INTR": [ { "value": "0xFFFFFFF9", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "C_NUM_SYNC_FF": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_IRQ_IS_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_KIND_OF_EDGE": [ { "value": "0xFFFFFFFF", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -38,7 +38,7 @@
         "C_IRQ_CONNECTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_INSTANCE": [ { "value": "design_1_microblaze_0_axi_intc_0", "resolve_type": "generated", "usage": "all" } ],
         "C_S_AXI_ADDR_WIDTH": [ { "value": "9", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
@@ -47,7 +47,7 @@
         "C_KIND_OF_INTR": [ { "value": "0xfffffff9", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_KIND_OF_EDGE": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_KIND_OF_LVL": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_ASYNC_INTR": [ { "value": "0xFFFFFFF8", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_ASYNC_INTR": [ { "value": "0xFFFFFFF9", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_NUM_SYNC_FF": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_IVAR_RESET_VALUE": [ { "value": "0x0000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
@@ -66,11 +66,11 @@
         "C_CASCADE_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -258,7 +258,7 @@
           "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
           "mode": "slave",
           "parameters": {
-            "SENSITIVITY": [ { "value": "LEVEL_HIGH:LEVEL_HIGH:EDGE_RISING", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "SENSITIVITY": [ { "value": "LEVEL_HIGH:LEVEL_HIGH:NULL", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "PortWidth": [ { "value": "3", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {

project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci

@@ -9,7 +9,7 @@
     "parameters": {
       "component_parameters": {
         "NUM_SI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "NUM_MI": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_MI": [ { "value": "9", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -325,11 +325,11 @@
         "Component_Name": [ { "value": "design_1_microblaze_0_axi_periph_0", "resolve_type": "user", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci

@@ -138,7 +138,7 @@
         "IN125_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "IN126_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "IN127_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "dout_width": [ { "value": "3", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ]
+        "dout_width": [ { "value": "3", "value_src": "user", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ]
       },
       "model_parameters": {
         "IN0_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -273,11 +273,11 @@
         "NUM_PORTS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xci

@@ -21,7 +21,7 @@
         "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -32,11 +32,11 @@
         "C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_s00_data_fifo_0/design_1_s00_data_fifo_0.xci

@@ -11,7 +11,7 @@
         "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
         "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
         "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "DATA_WIDTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -25,11 +25,11 @@
         "Component_Name": [ { "value": "design_1_s00_data_fifo_0", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -44,11 +44,11 @@
         "C_AXI_READ_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -84,8 +84,8 @@
         "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
         "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
         "s_axi_awready": [ { "direction": "out" } ],
-        "s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
-        "s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0xFFFFFFFFFFFFFFFF" } ],
         "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
         "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
         "s_axi_wready": [ { "direction": "out" } ],
@@ -103,8 +103,8 @@
         "m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
         "m_axi_awvalid": [ { "direction": "out" } ],
         "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
-        "m_axi_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
-        "m_axi_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
         "m_axi_wlast": [ { "direction": "out" } ],
         "m_axi_wvalid": [ { "direction": "out" } ],
         "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
@@ -118,30 +118,30 @@
           "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
           "mode": "slave",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_WSTRB": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BRESP": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -177,22 +177,22 @@
           "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
           "mode": "master",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_LOCK": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_CACHE": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_QOS": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -200,7 +200,7 @@
             "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_s01_data_fifo_0/design_1_s01_data_fifo_0.xci

@@ -11,7 +11,7 @@
         "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
         "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
         "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "DATA_WIDTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -25,11 +25,11 @@
         "Component_Name": [ { "value": "design_1_s01_data_fifo_0", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -44,11 +44,11 @@
         "C_AXI_READ_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -84,8 +84,8 @@
         "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
         "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
         "s_axi_awready": [ { "direction": "out" } ],
-        "s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
-        "s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0xFFFFFFFFFFFFFFFF" } ],
         "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
         "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
         "s_axi_wready": [ { "direction": "out" } ],
@@ -103,8 +103,8 @@
         "m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
         "m_axi_awvalid": [ { "direction": "out" } ],
         "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
-        "m_axi_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
-        "m_axi_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
         "m_axi_wlast": [ { "direction": "out" } ],
         "m_axi_wvalid": [ { "direction": "out" } ],
         "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
@@ -118,30 +118,30 @@
           "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
           "mode": "slave",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_WSTRB": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BRESP": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -177,22 +177,22 @@
           "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
           "mode": "master",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_LOCK": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_CACHE": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_QOS": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -200,7 +200,7 @@
             "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_s02_data_fifo_0/design_1_s02_data_fifo_0.xci

@@ -0,0 +1,268 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "design_1_s02_data_fifo_0",
+    "cell_name": "axi_interconnect_1/s02_couplers/s02_data_fifo",
+    "component_reference": "xilinx.com:ip:axi_data_fifo:2.1",
+    "ip_revision": "26",
+    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_s02_data_fifo_0",
+    "parameters": {
+      "component_parameters": {
+        "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "WRITE_FIFO_DEPTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "READ_FIFO_DEPTH": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "WRITE_FIFO_DELAY": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "READ_FIFO_DELAY": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "design_1_s02_data_fifo_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WRITE_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WRITE_FIFO_TYPE": [ { "value": "lut", "resolve_type": "generated", "usage": "all" } ],
+        "C_AXI_WRITE_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_READ_FIFO_DEPTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_READ_FIFO_TYPE": [ { "value": "lut", "resolve_type": "generated", "usage": "all" } ],
+        "C_AXI_READ_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "26" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_s02_data_fifo_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
+        "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
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+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
+        "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
+        "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0xFFFFFFFFFFFFFFFF" } ],
+        "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
+        "m_axi_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awvalid": [ { "direction": "out" } ],
+        "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "m_axi_wlast": [ { "direction": "out" } ],
+        "m_axi_wvalid": [ { "direction": "out" } ],
+        "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bready": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "s_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ]
+          }
+        },
+        "M_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "m_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "m_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "m_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "m_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "m_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready" } ]
+          }
+        },
+        "CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

project_1.srcs/sources_1/bd/design_1/ip/design_1_s03_data_fifo_0/design_1_s03_data_fifo_0.xci

@@ -0,0 +1,268 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "design_1_s03_data_fifo_0",
+    "cell_name": "axi_interconnect_1/s03_couplers/s03_data_fifo",
+    "component_reference": "xilinx.com:ip:axi_data_fifo:2.1",
+    "ip_revision": "26",
+    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_s03_data_fifo_0",
+    "parameters": {
+      "component_parameters": {
+        "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "WRITE_FIFO_DEPTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "READ_FIFO_DEPTH": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "WRITE_FIFO_DELAY": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "READ_FIFO_DELAY": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "design_1_s03_data_fifo_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WRITE_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WRITE_FIFO_TYPE": [ { "value": "lut", "resolve_type": "generated", "usage": "all" } ],
+        "C_AXI_WRITE_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_READ_FIFO_DEPTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_READ_FIFO_TYPE": [ { "value": "lut", "resolve_type": "generated", "usage": "all" } ],
+        "C_AXI_READ_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "26" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_s03_data_fifo_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
+        "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
+        "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
+        "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0xFFFFFFFFFFFFFFFF" } ],
+        "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
+        "m_axi_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_awvalid": [ { "direction": "out" } ],
+        "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "m_axi_wlast": [ { "direction": "out" } ],
+        "m_axi_wvalid": [ { "direction": "out" } ],
+        "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bready": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "s_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ]
+          }
+        },
+        "M_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "m_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "m_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "m_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "m_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "m_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready" } ]
+          }
+        },
+        "CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

project_1.srcs/sources_1/bd/design_1/ip/design_1_system_management_wiz_0_0/design_1_system_management_wiz_0_0.xci

@@ -9,7 +9,7 @@
     "parameters": {
       "component_parameters": {
         "Component_Name": [ { "value": "design_1_system_management_wiz_0_0", "resolve_type": "user", "usage": "all" } ],
-        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "VAUX0_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
         "VAUX1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
@@ -134,7 +134,7 @@
         "SEQUENCER_MODE": [ { "value": "Continuous", "resolve_type": "user", "usage": "all" } ],
         "ENABLE_CALIBRATION_AVERAGING": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "ENABLE_DRP": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_RESET": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ENABLE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "ENABLE_CONVST": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "ENABLE_CONVSTCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "ENABLE_CHANNEL": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -169,9 +169,9 @@
         "VBRAM_ALARM_LOWER": [ { "value": "0.86", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
         "VBRAM_ALARM_UPPER": [ { "value": "0.92", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
         "ENABLE_VCCPINT_ALARM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_VCCPSINTLP_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_VCCPSAUX_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ENABLE_VCCPSINTFP_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_VCCPSINTLP_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ENABLE_VCCPSAUX_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ENABLE_VCCPSINTFP_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "ENABLE_VCCPAUX_ALARM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "ENABLE_VCCDDRO_ALARM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "VCCDDRO_VOLT": [ { "value": "1_2", "resolve_type": "user", "usage": "all" } ],
@@ -205,14 +205,14 @@
         "DUAL_SEQ_TEMPERATURE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "CHANNEL_ENABLE_VCCINT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "DUAL_SEQ_VCCINT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "CHANNEL_ENABLE_VCCPSINTLP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CHANNEL_ENABLE_VCCPSINTLP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "AVERAGE_ENABLE_VCCPSINTLP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "DUAL_SEQ_VCCPSINTLP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "CHANNEL_ENABLE_VCCPSINTFP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CHANNEL_ENABLE_VCCPSINTFP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "AVERAGE_ENABLE_VCCPSINTFP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "DUAL_SEQ_VCCPSINTFP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "AVERAGE_ENABLE_VCCPSAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "CHANNEL_ENABLE_VCCPSAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CHANNEL_ENABLE_VCCPSAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "DUAL_SEQ_VCCPSAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "CHANNEL_ENABLE_VCCAUX": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "DUAL_SEQ_VCCAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -470,41 +470,41 @@
         "SELECT_USER_SUPPLY1_SLAVE2_SSIT_LEVEL": [ { "value": "0.9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "SELECT_USER_SUPPLY2_SLAVE2_SSIT_LEVEL": [ { "value": "1.8", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "SELECT_USER_SUPPLY3_SLAVE2_SSIT_LEVEL": [ { "value": "1.8", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "ANALOG_BANK_SELECTION": [ { "value": "28", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "VAUXN0_LOC": [ { "value": "B19", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP0_LOC": [ { "value": "B18", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN1_LOC": [ { "value": "C19", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP1_LOC": [ { "value": "C18", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN2_LOC": [ { "value": "G26", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP2_LOC": [ { "value": "G25", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN3_LOC": [ { "value": "D24", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP3_LOC": [ { "value": "E24", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN4_LOC": [ { "value": "F20", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP4_LOC": [ { "value": "G20", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN5_LOC": [ { "value": "H22", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP5_LOC": [ { "value": "H21", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN6_LOC": [ { "value": "H24", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP6_LOC": [ { "value": "J24", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN7_LOC": [ { "value": "K23", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP7_LOC": [ { "value": "K22", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN8_LOC": [ { "value": "A21", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP8_LOC": [ { "value": "A20", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN9_LOC": [ { "value": "A19", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP9_LOC": [ { "value": "A18", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN10_LOC": [ { "value": "C23", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP10_LOC": [ { "value": "D22", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN11_LOC": [ { "value": "C22", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP11_LOC": [ { "value": "C21", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN12_LOC": [ { "value": "D21", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP12_LOC": [ { "value": "D20", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN13_LOC": [ { "value": "D19", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP13_LOC": [ { "value": "E19", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN14_LOC": [ { "value": "H26", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP14_LOC": [ { "value": "J25", "resolve_type": "user", "usage": "all" } ],
-        "VAUXN15_LOC": [ { "value": "J22", "resolve_type": "user", "usage": "all" } ],
-        "VAUXP15_LOC": [ { "value": "J21", "resolve_type": "user", "usage": "all" } ],
-        "I2C_SCLK_LOC": [ { "value": "AC18", "resolve_type": "user", "usage": "all" } ],
-        "I2C_SDA_LOC": [ { "value": "AA19", "resolve_type": "user", "usage": "all" } ],
+        "ANALOG_BANK_SELECTION": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "VAUXN0_LOC": [ { "value": "B19", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP0_LOC": [ { "value": "B18", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN1_LOC": [ { "value": "C19", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP1_LOC": [ { "value": "C18", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN2_LOC": [ { "value": "G26", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP2_LOC": [ { "value": "G25", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN3_LOC": [ { "value": "D24", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP3_LOC": [ { "value": "E24", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN4_LOC": [ { "value": "F20", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP4_LOC": [ { "value": "G20", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN5_LOC": [ { "value": "H22", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP5_LOC": [ { "value": "H21", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN6_LOC": [ { "value": "H24", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP6_LOC": [ { "value": "J24", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN7_LOC": [ { "value": "K23", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP7_LOC": [ { "value": "K22", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN8_LOC": [ { "value": "A21", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP8_LOC": [ { "value": "A20", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN9_LOC": [ { "value": "A19", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP9_LOC": [ { "value": "A18", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN10_LOC": [ { "value": "C23", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP10_LOC": [ { "value": "D22", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN11_LOC": [ { "value": "C22", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP11_LOC": [ { "value": "C21", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN12_LOC": [ { "value": "D21", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP12_LOC": [ { "value": "D20", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN13_LOC": [ { "value": "D19", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP13_LOC": [ { "value": "E19", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN14_LOC": [ { "value": "H26", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP14_LOC": [ { "value": "J25", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXN15_LOC": [ { "value": "J22", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "VAUXP15_LOC": [ { "value": "J21", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "I2C_SCLK_LOC": [ { "value": "AC18", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "I2C_SDA_LOC": [ { "value": "AA19", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "EXTERNAL_MUXADDR_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "REFERENCE": [ { "value": "Internal", "resolve_type": "user", "usage": "all" } ],
         "UNDER_OT_ALARM": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -571,7 +571,7 @@
         "COMMON_N_SOURCE": [ { "value": "Vaux0", "resolve_type": "user", "enabled": false, "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_IS_DIABLO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_DUAL0_REGISTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_DUAL1_REGISTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -585,7 +585,7 @@
         "C_ENABLE_DUAL_SEQUENCE_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "c_component_name": [ { "value": "design_1_system_management_wiz_0_0", "resolve_type": "generated", "usage": "all" } ],
         "C_SIM_FILE_SEL": [ { "value": "Default", "resolve_type": "generated", "usage": "all" } ],
-        "C_SIM_DEVICE": [ { "value": "ZYNQ_ULTRASCALE", "resolve_type": "generated", "usage": "all" } ],
+        "C_SIM_DEVICE": [ { "value": "ULTRASCALE_PLUS", "resolve_type": "generated", "usage": "all" } ],
         "C_SIM_FILE_REL_PATH": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
         "C_SIM_FILE_NAME": [ { "value": "design", "resolve_type": "generated", "usage": "all" } ],
         "C_HAS_DCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -892,11 +892,11 @@
         "C_I2C_SDA_LOC": [ { "value": "AA19", "resolve_type": "generated", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci

@@ -30,11 +30,11 @@
         "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_3/design_1_xbar_3.xci

@@ -1,14 +1,14 @@
 {
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
-    "xci_name": "design_1_xbar_0",
+    "xci_name": "design_1_xbar_3",
     "cell_name": "axi_interconnect_0/xbar",
     "component_reference": "xilinx.com:ip:axi_crossbar:2.1",
     "ip_revision": "28",
-    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_0",
+    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_3",
     "parameters": {
       "component_parameters": {
-        "ADDR_RANGES": [ { "value": "5", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ADDR_RANGES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "NUM_SI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "NUM_MI": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -761,9 +761,9 @@
         "M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M04_A00_BASE_ADDR": [ { "value": "0x0000000080000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M04_A01_BASE_ADDR": [ { "value": "0x0000000080100000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "M04_A02_BASE_ADDR": [ { "value": "0x0000000080120000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "M04_A03_BASE_ADDR": [ { "value": "0x0000000081000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "M04_A04_BASE_ADDR": [ { "value": "0x0000000083000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "M04_A02_BASE_ADDR": [ { "value": "0x0000000083000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "M04_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M04_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M04_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M04_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -983,7 +983,7 @@
         "M01_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M01_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M01_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M02_A00_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M02_A00_ADDR_WIDTH": [ { "value": "12", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M02_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M02_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M02_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -1015,11 +1015,11 @@
         "M03_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M03_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M03_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M04_A00_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M04_A01_ADDR_WIDTH": [ { "value": "17", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M04_A02_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M04_A03_ADDR_WIDTH": [ { "value": "17", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M04_A04_ADDR_WIDTH": [ { "value": "24", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M04_A00_ADDR_WIDTH": [ { "value": "18", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M04_A01_ADDR_WIDTH": [ { "value": "18", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M04_A02_ADDR_WIDTH": [ { "value": "24", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M04_A03_ADDR_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M04_A04_ADDR_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M04_A05_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M04_A06_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M04_A07_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -1207,19 +1207,19 @@
         "M15_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M15_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M15_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Component_Name": [ { "value": "design_1_xbar_0", "resolve_type": "user", "usage": "all" } ]
+        "Component_Name": [ { "value": "design_1_xbar_3", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_NUM_SLAVE_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_NUM_MASTER_SLOTS": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_NUM_ADDR_RANGES": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_M_AXI_BASE_ADDR": [ { "value": "0x00000000830000000000000081000000000000008012000000000000801000000000000080000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040030000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040010000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_M_AXI_ADDR_WIDTH": [ { "value": "0x00000018000000110000001000000011000000100000000000000000000000000000000000000010000000000000000000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_NUM_ADDR_RANGES": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_BASE_ADDR": [ { "value": "0x000000008300000000000000801000000000000080000000ffffffffffffffffffffffffffffffff0000000040030000ffffffffffffffffffffffffffffffff0000000040010000ffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffff0000000040020000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_M_AXI_ADDR_WIDTH": [ { "value": "0x00000018000000120000001200000000000000000000001000000000000000000000000c000000000000000000000010000000000000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_S_AXI_BASE_ID": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_S_AXI_THREAD_ID_WIDTH": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -1241,11 +1241,11 @@
         "C_CONNECTIVITY_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -1259,9 +1259,9 @@
         "IPCONTEXT": [ { "value": "IP_Integrator" } ],
         "IPREVISION": [ { "value": "28" } ],
         "MANAGED": [ { "value": "TRUE" } ],
-        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_0" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_3" } ],
         "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
-        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
         "SWVERSION": [ { "value": "2022.2" } ],
         "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
       }

project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_4/design_1_xbar_4.xci

@@ -1,22 +1,22 @@
 {
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
-    "xci_name": "design_1_xbar_2",
+    "xci_name": "design_1_xbar_4",
     "cell_name": "axi_interconnect_1/xbar",
     "component_reference": "xilinx.com:ip:axi_crossbar:2.1",
     "ip_revision": "28",
-    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_2",
+    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_4",
     "parameters": {
       "component_parameters": {
         "ADDR_RANGES": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "NUM_SI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_SI": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "STRATEGY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
-        "DATA_WIDTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "CONNECTIVITY_MODE": [ { "value": "SAMD", "resolve_type": "user", "usage": "all" } ],
-        "ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -25,8 +25,8 @@
         "R_REGISTER": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "M00_S00_READ_CONNECTIVITY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M00_S01_READ_CONNECTIVITY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M00_S02_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M00_S03_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_S02_READ_CONNECTIVITY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_S03_READ_CONNECTIVITY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M00_S04_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M00_S05_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M00_S06_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -281,8 +281,8 @@
         "M15_S15_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M00_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M00_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M00_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M00_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M00_S04_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M00_S05_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M00_S06_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -537,8 +537,8 @@
         "M15_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S00_THREAD_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S01_THREAD_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "S02_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "S03_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S02_THREAD_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S03_THREAD_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S04_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S05_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S06_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -553,8 +553,8 @@
         "S15_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S00_WRITE_ACCEPTANCE": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S01_WRITE_ACCEPTANCE": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "S02_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "S03_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S02_WRITE_ACCEPTANCE": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S03_WRITE_ACCEPTANCE": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S04_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S05_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S06_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -569,8 +569,8 @@
         "S15_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S00_READ_ACCEPTANCE": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S01_READ_ACCEPTANCE": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "S02_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "S03_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S02_READ_ACCEPTANCE": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S03_READ_ACCEPTANCE": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S04_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S05_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "S06_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -1207,45 +1207,45 @@
         "M15_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M15_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M15_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Component_Name": [ { "value": "design_1_xbar_2", "resolve_type": "user", "usage": "all" } ]
+        "Component_Name": [ { "value": "design_1_xbar_4", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
-        "C_NUM_SLAVE_SLOTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_NUM_SLAVE_SLOTS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_NUM_MASTER_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_NUM_ADDR_RANGES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_M_AXI_BASE_ADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_M_AXI_ADDR_WIDTH": [ { "value": "0x00000028", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_S_AXI_BASE_ID": [ { "value": "0x0000000100000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_S_AXI_THREAD_ID_WIDTH": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
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+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
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         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
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+        "DEVICE": [ { "value": "xcku15p" } ],
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@@ -1259,9 +1259,9 @@
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+        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_4" } ],
         "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
-        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
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         "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
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+        "s_axi_bvalid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
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+        "s_axi_rresp": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
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+        "s_axi_rvalid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "s_axi_rready": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
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@@ -1319,16 +1319,16 @@
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-        "m_axi_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
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-        "m_axi_bid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_bid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
         "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
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-        "m_axi_arid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
+        "m_axi_arid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
         "m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
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@@ -1340,8 +1340,8 @@
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-        "m_axi_rdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
+        "m_axi_rid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_rdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
         "m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
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         "m_axi_rvalid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
@@ -1384,22 +1384,22 @@
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+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1417,7 +1417,7 @@
             "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
-            "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "0", "physical_right": "0" } ],
+            "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "1", "physical_right": "0" } ],
             "AWADDR": [ { "physical_name": "s_axi_awaddr", "physical_left": "39", "physical_right": "0" } ],
             "AWLEN": [ { "physical_name": "s_axi_awlen", "physical_left": "7", "physical_right": "0" } ],
             "AWSIZE": [ { "physical_name": "s_axi_awsize", "physical_left": "2", "physical_right": "0" } ],
@@ -1428,16 +1428,16 @@
             "AWQOS": [ { "physical_name": "s_axi_awqos", "physical_left": "3", "physical_right": "0" } ],
             "AWVALID": [ { "physical_name": "s_axi_awvalid", "physical_left": "0", "physical_right": "0" } ],
             "AWREADY": [ { "physical_name": "s_axi_awready", "physical_left": "0", "physical_right": "0" } ],
-            "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "255", "physical_right": "0" } ],
-            "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "31", "physical_right": "0" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "511", "physical_right": "0" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "63", "physical_right": "0" } ],
             "WLAST": [ { "physical_name": "s_axi_wlast", "physical_left": "0", "physical_right": "0" } ],
             "WVALID": [ { "physical_name": "s_axi_wvalid", "physical_left": "0", "physical_right": "0" } ],
             "WREADY": [ { "physical_name": "s_axi_wready", "physical_left": "0", "physical_right": "0" } ],
-            "BID": [ { "physical_name": "s_axi_bid", "physical_left": "0", "physical_right": "0" } ],
+            "BID": [ { "physical_name": "s_axi_bid", "physical_left": "1", "physical_right": "0" } ],
             "BRESP": [ { "physical_name": "s_axi_bresp", "physical_left": "1", "physical_right": "0" } ],
             "BVALID": [ { "physical_name": "s_axi_bvalid", "physical_left": "0", "physical_right": "0" } ],
             "BREADY": [ { "physical_name": "s_axi_bready", "physical_left": "0", "physical_right": "0" } ],
-            "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "0", "physical_right": "0" } ],
+            "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "1", "physical_right": "0" } ],
             "ARADDR": [ { "physical_name": "s_axi_araddr", "physical_left": "39", "physical_right": "0" } ],
             "ARLEN": [ { "physical_name": "s_axi_arlen", "physical_left": "7", "physical_right": "0" } ],
             "ARSIZE": [ { "physical_name": "s_axi_arsize", "physical_left": "2", "physical_right": "0" } ],
@@ -1448,8 +1448,8 @@
             "ARQOS": [ { "physical_name": "s_axi_arqos", "physical_left": "3", "physical_right": "0" } ],
             "ARVALID": [ { "physical_name": "s_axi_arvalid", "physical_left": "0", "physical_right": "0" } ],
             "ARREADY": [ { "physical_name": "s_axi_arready", "physical_left": "0", "physical_right": "0" } ],
-            "RID": [ { "physical_name": "s_axi_rid", "physical_left": "0", "physical_right": "0" } ],
-            "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "255", "physical_right": "0" } ],
+            "RID": [ { "physical_name": "s_axi_rid", "physical_left": "1", "physical_right": "0" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "511", "physical_right": "0" } ],
             "RRESP": [ { "physical_name": "s_axi_rresp", "physical_left": "1", "physical_right": "0" } ],
             "RLAST": [ { "physical_name": "s_axi_rlast", "physical_left": "0", "physical_right": "0" } ],
             "RVALID": [ { "physical_name": "s_axi_rvalid", "physical_left": "0", "physical_right": "0" } ],
@@ -1461,10 +1461,10 @@
           "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
           "mode": "master",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "512", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1472,11 +1472,11 @@
             "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_REGION": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1494,7 +1494,7 @@
             "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
-            "AWID": [ { "physical_name": "m_axi_awid", "physical_left": "0", "physical_right": "0" } ],
+            "AWID": [ { "physical_name": "m_axi_awid", "physical_left": "1", "physical_right": "0" } ],
             "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "39", "physical_right": "0" } ],
             "AWLEN": [ { "physical_name": "m_axi_awlen", "physical_left": "7", "physical_right": "0" } ],
             "AWSIZE": [ { "physical_name": "m_axi_awsize", "physical_left": "2", "physical_right": "0" } ],
@@ -1506,16 +1506,16 @@
             "AWQOS": [ { "physical_name": "m_axi_awqos", "physical_left": "3", "physical_right": "0" } ],
             "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "0", "physical_right": "0" } ],
             "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "0", "physical_right": "0" } ],
-            "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "255", "physical_right": "0" } ],
-            "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "31", "physical_right": "0" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "511", "physical_right": "0" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "63", "physical_right": "0" } ],
             "WLAST": [ { "physical_name": "m_axi_wlast", "physical_left": "0", "physical_right": "0" } ],
             "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "0", "physical_right": "0" } ],
             "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "0", "physical_right": "0" } ],
-            "BID": [ { "physical_name": "m_axi_bid", "physical_left": "0", "physical_right": "0" } ],
+            "BID": [ { "physical_name": "m_axi_bid", "physical_left": "1", "physical_right": "0" } ],
             "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "1", "physical_right": "0" } ],
             "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "0", "physical_right": "0" } ],
             "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "0", "physical_right": "0" } ],
-            "ARID": [ { "physical_name": "m_axi_arid", "physical_left": "0", "physical_right": "0" } ],
+            "ARID": [ { "physical_name": "m_axi_arid", "physical_left": "1", "physical_right": "0" } ],
             "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "39", "physical_right": "0" } ],
             "ARLEN": [ { "physical_name": "m_axi_arlen", "physical_left": "7", "physical_right": "0" } ],
             "ARSIZE": [ { "physical_name": "m_axi_arsize", "physical_left": "2", "physical_right": "0" } ],
@@ -1527,8 +1527,8 @@
             "ARQOS": [ { "physical_name": "m_axi_arqos", "physical_left": "3", "physical_right": "0" } ],
             "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "0", "physical_right": "0" } ],
             "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "0", "physical_right": "0" } ],
-            "RID": [ { "physical_name": "m_axi_rid", "physical_left": "0", "physical_right": "0" } ],
-            "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "255", "physical_right": "0" } ],
+            "RID": [ { "physical_name": "m_axi_rid", "physical_left": "1", "physical_right": "0" } ],
+            "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "511", "physical_right": "0" } ],
             "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "1", "physical_right": "0" } ],
             "RLAST": [ { "physical_name": "m_axi_rlast", "physical_left": "0", "physical_right": "0" } ],
             "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "0", "physical_right": "0" } ],
@@ -1540,22 +1540,22 @@
           "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
           "mode": "slave",
           "parameters": {
-            "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1573,7 +1573,7 @@
             "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
-            "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "1", "physical_right": "1" } ],
+            "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "3", "physical_right": "2" } ],
             "AWADDR": [ { "physical_name": "s_axi_awaddr", "physical_left": "79", "physical_right": "40" } ],
             "AWLEN": [ { "physical_name": "s_axi_awlen", "physical_left": "15", "physical_right": "8" } ],
             "AWSIZE": [ { "physical_name": "s_axi_awsize", "physical_left": "5", "physical_right": "3" } ],
@@ -1584,16 +1584,16 @@
             "AWQOS": [ { "physical_name": "s_axi_awqos", "physical_left": "7", "physical_right": "4" } ],
             "AWVALID": [ { "physical_name": "s_axi_awvalid", "physical_left": "1", "physical_right": "1" } ],
             "AWREADY": [ { "physical_name": "s_axi_awready", "physical_left": "1", "physical_right": "1" } ],
-            "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "511", "physical_right": "256" } ],
-            "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "63", "physical_right": "32" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "1023", "physical_right": "512" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "127", "physical_right": "64" } ],
             "WLAST": [ { "physical_name": "s_axi_wlast", "physical_left": "1", "physical_right": "1" } ],
             "WVALID": [ { "physical_name": "s_axi_wvalid", "physical_left": "1", "physical_right": "1" } ],
             "WREADY": [ { "physical_name": "s_axi_wready", "physical_left": "1", "physical_right": "1" } ],
-            "BID": [ { "physical_name": "s_axi_bid", "physical_left": "1", "physical_right": "1" } ],
+            "BID": [ { "physical_name": "s_axi_bid", "physical_left": "3", "physical_right": "2" } ],
             "BRESP": [ { "physical_name": "s_axi_bresp", "physical_left": "3", "physical_right": "2" } ],
             "BVALID": [ { "physical_name": "s_axi_bvalid", "physical_left": "1", "physical_right": "1" } ],
             "BREADY": [ { "physical_name": "s_axi_bready", "physical_left": "1", "physical_right": "1" } ],
-            "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "1", "physical_right": "1" } ],
+            "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "3", "physical_right": "2" } ],
             "ARADDR": [ { "physical_name": "s_axi_araddr", "physical_left": "79", "physical_right": "40" } ],
             "ARLEN": [ { "physical_name": "s_axi_arlen", "physical_left": "15", "physical_right": "8" } ],
             "ARSIZE": [ { "physical_name": "s_axi_arsize", "physical_left": "5", "physical_right": "3" } ],
@@ -1604,13 +1604,167 @@
             "ARQOS": [ { "physical_name": "s_axi_arqos", "physical_left": "7", "physical_right": "4" } ],
             "ARVALID": [ { "physical_name": "s_axi_arvalid", "physical_left": "1", "physical_right": "1" } ],
             "ARREADY": [ { "physical_name": "s_axi_arready", "physical_left": "1", "physical_right": "1" } ],
-            "RID": [ { "physical_name": "s_axi_rid", "physical_left": "1", "physical_right": "1" } ],
-            "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "511", "physical_right": "256" } ],
+            "RID": [ { "physical_name": "s_axi_rid", "physical_left": "3", "physical_right": "2" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "1023", "physical_right": "512" } ],
             "RRESP": [ { "physical_name": "s_axi_rresp", "physical_left": "3", "physical_right": "2" } ],
             "RLAST": [ { "physical_name": "s_axi_rlast", "physical_left": "1", "physical_right": "1" } ],
             "RVALID": [ { "physical_name": "s_axi_rvalid", "physical_left": "1", "physical_right": "1" } ],
             "RREADY": [ { "physical_name": "s_axi_rready", "physical_left": "1", "physical_right": "1" } ]
           }
+        },
+        "S02_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "5", "physical_right": "4" } ],
+            "AWADDR": [ { "physical_name": "s_axi_awaddr", "physical_left": "119", "physical_right": "80" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen", "physical_left": "23", "physical_right": "16" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize", "physical_left": "8", "physical_right": "6" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst", "physical_left": "5", "physical_right": "4" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock", "physical_left": "2", "physical_right": "2" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache", "physical_left": "11", "physical_right": "8" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot", "physical_left": "8", "physical_right": "6" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos", "physical_left": "11", "physical_right": "8" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid", "physical_left": "2", "physical_right": "2" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready", "physical_left": "2", "physical_right": "2" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "1535", "physical_right": "1024" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "191", "physical_right": "128" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast", "physical_left": "2", "physical_right": "2" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid", "physical_left": "2", "physical_right": "2" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready", "physical_left": "2", "physical_right": "2" } ],
+            "BID": [ { "physical_name": "s_axi_bid", "physical_left": "5", "physical_right": "4" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp", "physical_left": "5", "physical_right": "4" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid", "physical_left": "2", "physical_right": "2" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready", "physical_left": "2", "physical_right": "2" } ],
+            "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "5", "physical_right": "4" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr", "physical_left": "119", "physical_right": "80" } ],
+            "ARLEN": [ { "physical_name": "s_axi_arlen", "physical_left": "23", "physical_right": "16" } ],
+            "ARSIZE": [ { "physical_name": "s_axi_arsize", "physical_left": "8", "physical_right": "6" } ],
+            "ARBURST": [ { "physical_name": "s_axi_arburst", "physical_left": "5", "physical_right": "4" } ],
+            "ARLOCK": [ { "physical_name": "s_axi_arlock", "physical_left": "2", "physical_right": "2" } ],
+            "ARCACHE": [ { "physical_name": "s_axi_arcache", "physical_left": "11", "physical_right": "8" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot", "physical_left": "8", "physical_right": "6" } ],
+            "ARQOS": [ { "physical_name": "s_axi_arqos", "physical_left": "11", "physical_right": "8" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid", "physical_left": "2", "physical_right": "2" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready", "physical_left": "2", "physical_right": "2" } ],
+            "RID": [ { "physical_name": "s_axi_rid", "physical_left": "5", "physical_right": "4" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "1535", "physical_right": "1024" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp", "physical_left": "5", "physical_right": "4" } ],
+            "RLAST": [ { "physical_name": "s_axi_rlast", "physical_left": "2", "physical_right": "2" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid", "physical_left": "2", "physical_right": "2" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready", "physical_left": "2", "physical_right": "2" } ]
+          }
+        },
+        "S03_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "7", "physical_right": "6" } ],
+            "AWADDR": [ { "physical_name": "s_axi_awaddr", "physical_left": "159", "physical_right": "120" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen", "physical_left": "31", "physical_right": "24" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize", "physical_left": "11", "physical_right": "9" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst", "physical_left": "7", "physical_right": "6" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock", "physical_left": "3", "physical_right": "3" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache", "physical_left": "15", "physical_right": "12" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot", "physical_left": "11", "physical_right": "9" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos", "physical_left": "15", "physical_right": "12" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid", "physical_left": "3", "physical_right": "3" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready", "physical_left": "3", "physical_right": "3" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "2047", "physical_right": "1536" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "255", "physical_right": "192" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast", "physical_left": "3", "physical_right": "3" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid", "physical_left": "3", "physical_right": "3" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready", "physical_left": "3", "physical_right": "3" } ],
+            "BID": [ { "physical_name": "s_axi_bid", "physical_left": "7", "physical_right": "6" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp", "physical_left": "7", "physical_right": "6" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid", "physical_left": "3", "physical_right": "3" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready", "physical_left": "3", "physical_right": "3" } ],
+            "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "7", "physical_right": "6" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr", "physical_left": "159", "physical_right": "120" } ],
+            "ARLEN": [ { "physical_name": "s_axi_arlen", "physical_left": "31", "physical_right": "24" } ],
+            "ARSIZE": [ { "physical_name": "s_axi_arsize", "physical_left": "11", "physical_right": "9" } ],
+            "ARBURST": [ { "physical_name": "s_axi_arburst", "physical_left": "7", "physical_right": "6" } ],
+            "ARLOCK": [ { "physical_name": "s_axi_arlock", "physical_left": "3", "physical_right": "3" } ],
+            "ARCACHE": [ { "physical_name": "s_axi_arcache", "physical_left": "15", "physical_right": "12" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot", "physical_left": "11", "physical_right": "9" } ],
+            "ARQOS": [ { "physical_name": "s_axi_arqos", "physical_left": "15", "physical_right": "12" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid", "physical_left": "3", "physical_right": "3" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready", "physical_left": "3", "physical_right": "3" } ],
+            "RID": [ { "physical_name": "s_axi_rid", "physical_left": "7", "physical_right": "6" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "2047", "physical_right": "1536" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp", "physical_left": "7", "physical_right": "6" } ],
+            "RLAST": [ { "physical_name": "s_axi_rlast", "physical_left": "3", "physical_right": "3" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid", "physical_left": "3", "physical_right": "3" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready", "physical_left": "3", "physical_right": "3" } ]
+          }
         }
       }
     }

project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_5/design_1_xbar_5.xci

@@ -1,16 +1,16 @@
 {
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
-    "xci_name": "design_1_xbar_1",
+    "xci_name": "design_1_xbar_5",
     "cell_name": "microblaze_0_axi_periph/xbar",
     "component_reference": "xilinx.com:ip:axi_crossbar:2.1",
     "ip_revision": "28",
-    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_1",
+    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_5",
     "parameters": {
       "component_parameters": {
         "ADDR_RANGES": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "NUM_SI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "NUM_MI": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_MI": [ { "value": "9", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "STRATEGY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@@ -135,8 +135,8 @@
         "M06_S13_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M06_S14_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M06_S15_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M07_S00_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M07_S01_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_S00_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_S01_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_S02_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_S03_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_S04_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -151,8 +151,8 @@
         "M07_S13_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_S14_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_S15_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M08_S00_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M08_S01_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M08_S00_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M08_S01_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M08_S02_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M08_S03_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M08_S04_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -391,8 +391,8 @@
         "M06_S13_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M06_S14_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M06_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M07_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M07_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_S04_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -407,8 +407,8 @@
         "M07_S13_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_S14_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M08_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M08_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M08_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M08_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M08_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M08_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M08_S04_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -590,8 +590,8 @@
         "M04_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "M05_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "M06_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
-        "M07_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M08_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "M08_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "M09_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M10_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M11_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -606,8 +606,8 @@
         "M04_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "M05_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "M06_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
-        "M07_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M08_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "M08_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "M09_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M10_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M11_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -727,7 +727,7 @@
         "M01_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M01_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M01_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "M02_A00_BASE_ADDR": [ { "value": "0x0000000081000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "M02_A00_BASE_ADDR": [ { "value": "0x0000000080100000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M02_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M02_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M02_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -743,7 +743,7 @@
         "M02_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M02_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M02_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "M03_A00_BASE_ADDR": [ { "value": "0x0000000081010000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "M03_A00_BASE_ADDR": [ { "value": "0x0000000080110000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M03_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M03_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M03_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -759,7 +759,7 @@
         "M03_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M03_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "M04_A00_BASE_ADDR": [ { "value": "0x0000000080100000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "M04_A00_BASE_ADDR": [ { "value": "0x0000000080010000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M04_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M04_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -775,7 +775,7 @@
         "M04_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M04_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M04_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "M05_A00_BASE_ADDR": [ { "value": "0x0000000080110000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "M05_A00_BASE_ADDR": [ { "value": "0x0000000080020000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M05_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M05_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M05_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -791,7 +791,7 @@
         "M05_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M05_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M05_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "M06_A00_BASE_ADDR": [ { "value": "0x0000000080120000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "M06_A00_BASE_ADDR": [ { "value": "0x0000000080030000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M06_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M06_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M06_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -807,7 +807,7 @@
         "M06_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M06_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M06_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "M07_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "M07_A00_BASE_ADDR": [ { "value": "0x0000000080120000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M07_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M07_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M07_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -823,7 +823,7 @@
         "M07_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M07_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M07_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "M08_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "M08_A00_BASE_ADDR": [ { "value": "0x0000000080130000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M08_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M08_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "M08_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -1063,7 +1063,7 @@
         "M06_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M06_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M06_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M07_A00_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M07_A00_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -1079,7 +1079,7 @@
         "M07_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M07_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "M08_A00_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M08_A00_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M08_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M08_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M08_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -1207,19 +1207,19 @@
         "M15_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M15_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "M15_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Component_Name": [ { "value": "design_1_xbar_1", "resolve_type": "user", "usage": "all" } ]
+        "Component_Name": [ { "value": "design_1_xbar_5", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_NUM_SLAVE_SLOTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_NUM_MASTER_SLOTS": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_MASTER_SLOTS": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_NUM_ADDR_RANGES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_M_AXI_BASE_ADDR": [ { "value": "0x0000000080120000000000008011000000000000801000000000000081010000000000008100000000000000800000000000000083000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_M_AXI_ADDR_WIDTH": [ { "value": "0x00000010000000100000001000000010000000100000001000000018", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_M_AXI_BASE_ADDR": [ { "value": "0x000000008013000000000000801200000000000080030000000000008002000000000000800100000000000080110000000000008010000000000000800000000000000083000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_M_AXI_ADDR_WIDTH": [ { "value": "0x000000100000001000000010000000100000001000000010000000100000001000000018", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_S_AXI_BASE_ID": [ { "value": "0x0000000100000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_S_AXI_THREAD_ID_WIDTH": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -1228,24 +1228,24 @@
         "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_M_AXI_WRITE_CONNECTIVITY": [ { "value": "0x00000003000000030000000300000003000000030000000300000003", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_M_AXI_READ_CONNECTIVITY": [ { "value": "0x00000003000000030000000300000003000000030000000300000003", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_M_AXI_WRITE_CONNECTIVITY": [ { "value": "0x000000030000000300000003000000030000000300000003000000030000000300000003", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_M_AXI_READ_CONNECTIVITY": [ { "value": "0x000000030000000300000003000000030000000300000003000000030000000300000003", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_R_REGISTER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S_AXI_SINGLE_THREAD": [ { "value": "0x0000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_S_AXI_WRITE_ACCEPTANCE": [ { "value": "0x0000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_S_AXI_READ_ACCEPTANCE": [ { "value": "0x0000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_M_AXI_WRITE_ISSUING": [ { "value": "0x00000001000000010000000100000001000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_M_AXI_READ_ISSUING": [ { "value": "0x00000001000000010000000100000001000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_M_AXI_WRITE_ISSUING": [ { "value": "0x000000010000000100000001000000010000000100000001000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_M_AXI_READ_ISSUING": [ { "value": "0x000000010000000100000001000000010000000100000001000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_S_AXI_ARB_PRIORITY": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_M_AXI_SECURE": [ { "value": "0x00000000000000000000000000000000000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_M_AXI_SECURE": [ { "value": "0x000000000000000000000000000000000000000000000000000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_CONNECTIVITY_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -1259,9 +1259,9 @@
         "IPCONTEXT": [ { "value": "IP_Integrator" } ],
         "IPREVISION": [ { "value": "28" } ],
         "MANAGED": [ { "value": "TRUE" } ],
-        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_1" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_5" } ],
         "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
-        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
         "SWVERSION": [ { "value": "2022.2" } ],
         "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
       }
@@ -1289,25 +1289,25 @@
         "s_axi_rresp": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
         "s_axi_rvalid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
         "s_axi_rready": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
-        "m_axi_awaddr": [ { "direction": "out", "size_left": "279", "size_right": "0" } ],
-        "m_axi_awprot": [ { "direction": "out", "size_left": "20", "size_right": "0" } ],
-        "m_axi_awvalid": [ { "direction": "out", "size_left": "6", "size_right": "0" } ],
-        "m_axi_awready": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x00" } ],
-        "m_axi_wdata": [ { "direction": "out", "size_left": "223", "size_right": "0" } ],
-        "m_axi_wstrb": [ { "direction": "out", "size_left": "27", "size_right": "0" } ],
-        "m_axi_wvalid": [ { "direction": "out", "size_left": "6", "size_right": "0" } ],
-        "m_axi_wready": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x00" } ],
-        "m_axi_bresp": [ { "direction": "in", "size_left": "13", "size_right": "0", "driver_value": "0x0000" } ],
-        "m_axi_bvalid": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x00" } ],
-        "m_axi_bready": [ { "direction": "out", "size_left": "6", "size_right": "0" } ],
-        "m_axi_araddr": [ { "direction": "out", "size_left": "279", "size_right": "0" } ],
-        "m_axi_arprot": [ { "direction": "out", "size_left": "20", "size_right": "0" } ],
-        "m_axi_arvalid": [ { "direction": "out", "size_left": "6", "size_right": "0" } ],
-        "m_axi_arready": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x00" } ],
-        "m_axi_rdata": [ { "direction": "in", "size_left": "223", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000" } ],
-        "m_axi_rresp": [ { "direction": "in", "size_left": "13", "size_right": "0", "driver_value": "0x0000" } ],
-        "m_axi_rvalid": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x00" } ],
-        "m_axi_rready": [ { "direction": "out", "size_left": "6", "size_right": "0" } ]
+        "m_axi_awaddr": [ { "direction": "out", "size_left": "359", "size_right": "0" } ],
+        "m_axi_awprot": [ { "direction": "out", "size_left": "26", "size_right": "0" } ],
+        "m_axi_awvalid": [ { "direction": "out", "size_left": "8", "size_right": "0" } ],
+        "m_axi_awready": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0x000" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "287", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "35", "size_right": "0" } ],
+        "m_axi_wvalid": [ { "direction": "out", "size_left": "8", "size_right": "0" } ],
+        "m_axi_wready": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0x000" } ],
+        "m_axi_bresp": [ { "direction": "in", "size_left": "17", "size_right": "0", "driver_value": "0x00000" } ],
+        "m_axi_bvalid": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0x000" } ],
+        "m_axi_bready": [ { "direction": "out", "size_left": "8", "size_right": "0" } ],
+        "m_axi_araddr": [ { "direction": "out", "size_left": "359", "size_right": "0" } ],
+        "m_axi_arprot": [ { "direction": "out", "size_left": "26", "size_right": "0" } ],
+        "m_axi_arvalid": [ { "direction": "out", "size_left": "8", "size_right": "0" } ],
+        "m_axi_arready": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0x000" } ],
+        "m_axi_rdata": [ { "direction": "in", "size_left": "287", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000000000000000" } ],
+        "m_axi_rresp": [ { "direction": "in", "size_left": "17", "size_right": "0", "driver_value": "0x00000" } ],
+        "m_axi_rvalid": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0x000" } ],
+        "m_axi_rready": [ { "direction": "out", "size_left": "8", "size_right": "0" } ]
       },
       "interfaces": {
         "RSTIF": {
@@ -1486,7 +1486,7 @@
             "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
-            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
             "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1871,6 +1871,124 @@
             "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "6", "physical_right": "6" } ],
             "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "6", "physical_right": "6" } ]
           }
+        },
+        "M07_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "319", "physical_right": "280" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot", "physical_left": "23", "physical_right": "21" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "7", "physical_right": "7" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "7", "physical_right": "7" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "255", "physical_right": "224" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "31", "physical_right": "28" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "7", "physical_right": "7" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "7", "physical_right": "7" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "15", "physical_right": "14" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "7", "physical_right": "7" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "7", "physical_right": "7" } ],
+            "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "319", "physical_right": "280" } ],
+            "ARPROT": [ { "physical_name": "m_axi_arprot", "physical_left": "23", "physical_right": "21" } ],
+            "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "7", "physical_right": "7" } ],
+            "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "7", "physical_right": "7" } ],
+            "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "255", "physical_right": "224" } ],
+            "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "15", "physical_right": "14" } ],
+            "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "7", "physical_right": "7" } ],
+            "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "7", "physical_right": "7" } ]
+          }
+        },
+        "M08_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "359", "physical_right": "320" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot", "physical_left": "26", "physical_right": "24" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "8", "physical_right": "8" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "8", "physical_right": "8" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "287", "physical_right": "256" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "35", "physical_right": "32" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "8", "physical_right": "8" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "8", "physical_right": "8" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "17", "physical_right": "16" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "8", "physical_right": "8" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "8", "physical_right": "8" } ],
+            "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "359", "physical_right": "320" } ],
+            "ARPROT": [ { "physical_name": "m_axi_arprot", "physical_left": "26", "physical_right": "24" } ],
+            "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "8", "physical_right": "8" } ],
+            "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "8", "physical_right": "8" } ],
+            "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "287", "physical_right": "256" } ],
+            "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "17", "physical_right": "16" } ],
+            "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "8", "physical_right": "8" } ],
+            "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "8", "physical_right": "8" } ]
+          }
         }
       }
     }

project_1.srcs/sources_1/bd/design_1/ip/design_1_xdma_0_0/design_1_xdma_0_0.xci

@@ -12,38 +12,38 @@
         "functional_mode": [ { "value": "AXI_Bridge", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "mode_selection": [ { "value": "Advanced", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "device_port_type": [ { "value": "PCI_Express_Endpoint_device", "resolve_type": "user", "usage": "all" } ],
-        "pcie_blk_locn": [ { "value": "X0Y0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "pl_link_cap_max_link_width": [ { "value": "X8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "pcie_blk_locn": [ { "value": "X0Y2", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "pl_link_cap_max_link_width": [ { "value": "X16", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "pl_link_cap_max_link_speed": [ { "value": "8.0_GT/s", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "ref_clk_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ],
         "drp_clk_sel": [ { "value": "Internal", "resolve_type": "user", "usage": "all" } ],
         "free_run_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ],
         "axi_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "axi_data_width": [ { "value": "256_bit", "resolve_type": "user", "usage": "all" } ],
-        "axisten_freq": [ { "value": "250", "resolve_type": "user", "usage": "all" } ],
+        "axi_data_width": [ { "value": "512_bit", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "axisten_freq": [ { "value": "250", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "en_axi_slave_if": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "en_axi_master_if": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "pipe_sim": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "en_ext_ch_gt_drp": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "en_pcie_drp": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "dedicate_perst": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "dedicate_perst": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "sys_reset_polarity": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "mcap_enablement": [ { "value": "None", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "mcap_fpga_bitstream_version": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "ext_startup_primitive": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "enable_code": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
         "vendor_id": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ],
-        "pf0_device_id": [ { "value": "9038", "resolve_type": "user", "usage": "all" } ],
+        "pf0_device_id": [ { "value": "903F", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "pf0_revision_id": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
         "pf0_subsystem_vendor_id": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ],
         "pf0_subsystem_id": [ { "value": "0007", "resolve_type": "user", "usage": "all" } ],
         "pf0_Use_Class_Code_Lookup_Assistant": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
         "pf0_base_class_menu": [ { "value": "Memory_controller", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "pf0_class_code_base": [ { "value": "05", "resolve_type": "user", "usage": "all" } ],
+        "pf0_class_code_base": [ { "value": "05", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "pf0_sub_class_interface_menu": [ { "value": "Other_memory_controller", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "pf0_class_code_sub": [ { "value": "80", "resolve_type": "user", "usage": "all" } ],
-        "pf0_class_code_interface": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
-        "pf0_class_code": [ { "value": "058000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "pf0_class_code_sub": [ { "value": "80", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "pf0_class_code_interface": [ { "value": "00", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "pf0_class_code": [ { "value": "058000", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "axilite_master_en": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
         "axilite_master_size": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "axilite_master_scale": [ { "value": "Megabytes", "resolve_type": "user", "enabled": false, "usage": "all" } ],
@@ -74,7 +74,7 @@
         "en_transceiver_status_ports": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "xdma_rnum_chnl": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
         "xdma_wnum_chnl": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
-        "xdma_axilite_slave": [ { "value": "true", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "xdma_axilite_slave": [ { "value": "true", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "xdma_num_usr_irq": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
         "xdma_rnum_rids": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "xdma_wnum_rids": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -82,13 +82,13 @@
         "PCIE_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
         "EGW_IS_PARENT_IP": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
         "en_gt_selection": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "select_quad": [ { "value": "GTH_Quad_224", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "select_quad": [ { "value": "GTY_Quad_130", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "RX_PPM_OFFSET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "INS_LOSS_NYQ": [ { "value": "15", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "PHY_LP_TXPRESET": [ { "value": "4", "resolve_type": "user", "usage": "all" } ],
-        "coreclk_freq": [ { "value": "500", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "plltype": [ { "value": "QPLL1", "resolve_type": "user", "usage": "all" } ],
+        "coreclk_freq": [ { "value": "500", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "plltype": [ { "value": "QPLL1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "xdma_axi_intf_mm": [ { "value": "AXI_Memory_Mapped", "resolve_type": "user", "usage": "all" } ],
         "xdma_pcie_64bit_en": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "silicon_rev": [ { "value": "Pre-Production", "resolve_type": "user", "usage": "all" } ],
@@ -153,7 +153,7 @@
         "include_baroffset_reg": [ { "value": "true", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "BASEADDR": [ { "value": "0x83000000", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
         "HIGHADDR": [ { "value": "0x83FFFFFF", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
-        "s_axi_id_width": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "s_axi_id_width": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "c_m_axi_num_write": [ { "value": "8", "resolve_type": "user", "usage": "all" } ],
         "c_m_axi_num_read": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "c_m_axi_num_readq": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
@@ -163,9 +163,9 @@
         "axi_aclk_loopback": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "pf0_bar0_enabled": [ { "value": "true", "resolve_type": "user", "usage": "all" } ],
         "pf0_bar0_type": [ { "value": "Memory", "resolve_type": "user", "usage": "all" } ],
-        "pf0_bar0_size": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "pf0_bar0_size": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "pf0_bar0_scale": [ { "value": "Megabytes", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "pf0_bar0_64bit": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
+        "pf0_bar0_64bit": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "pf0_bar0_prefetchable": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "pf0_bar1_enabled": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
         "pf0_bar1_type": [ { "value": "Memory", "resolve_type": "user", "enabled": false, "usage": "all" } ],
@@ -722,10 +722,10 @@
         "pf1_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "pf2_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "pf3_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "PF0_DEVICE_ID_mqdma": [ { "value": "9038", "resolve_type": "user", "usage": "all" } ],
+        "PF0_DEVICE_ID_mqdma": [ { "value": "903F", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "PF1_DEVICE_ID_mqdma": [ { "value": "0007", "resolve_type": "user", "usage": "all" } ],
-        "PF2_DEVICE_ID_mqdma": [ { "value": "9238", "resolve_type": "user", "usage": "all" } ],
-        "PF3_DEVICE_ID_mqdma": [ { "value": "9338", "resolve_type": "user", "usage": "all" } ],
+        "PF2_DEVICE_ID_mqdma": [ { "value": "923F", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PF3_DEVICE_ID_mqdma": [ { "value": "933F", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "PF0_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
         "PF1_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
         "PF2_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
@@ -771,26 +771,26 @@
         "PF0_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF0_SRIOV_FUNC_DEP_LINK": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
         "PF0_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
-        "PF0_SRIOV_VF_DEVICE_ID": [ { "value": "A038", "resolve_type": "user", "usage": "all" } ],
+        "PF0_SRIOV_VF_DEVICE_ID": [ { "value": "A03F", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "PF0_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
         "PF1_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF1_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF1_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
         "PF1_SRIOV_FUNC_DEP_LINK": [ { "value": "0001", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF1_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
-        "PF1_SRIOV_VF_DEVICE_ID": [ { "value": "A138", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "PF1_SRIOV_VF_DEVICE_ID": [ { "value": "A13F", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF2_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF2_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF2_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
         "PF2_SRIOV_FUNC_DEP_LINK": [ { "value": "0002", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF2_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
-        "PF2_SRIOV_VF_DEVICE_ID": [ { "value": "A238", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "PF2_SRIOV_VF_DEVICE_ID": [ { "value": "A23F", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF3_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF3_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF3_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
         "PF3_SRIOV_FUNC_DEP_LINK": [ { "value": "0003", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "PF3_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
-        "PF3_SRIOV_VF_DEVICE_ID": [ { "value": "A338", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "PF3_SRIOV_VF_DEVICE_ID": [ { "value": "A33F", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "pf0_ari_enabled": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
         "pf0_msix_enabled_mqdma": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
         "pf1_msix_enabled_mqdma": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
@@ -942,12 +942,12 @@
         "enable_error_injection": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "performance_exdes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "descriptor_bypass_exdes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "vdm_en": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "vdm_en": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "virtio_exdes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "virtio_perf_exdes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "bridge_burst": [ { "value": "true", "resolve_type": "user", "usage": "all" } ],
+        "bridge_burst": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "insert_cips": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
-        "en_bridge_slv": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "en_bridge_slv": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "enable_clock_delay_grp": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "replace_uram_with_bram": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "errc_dec_en": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -961,28 +961,28 @@
         "COMPONENT_NAME": [ { "value": "xdma_0", "resolve_type": "generated", "usage": "all" } ],
         "PL_UPSTREAM_FACING": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ],
         "TL_LEGACY_MODE_ENABLE": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
-        "PCIE_BLK_LOCN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "PL_LINK_CAP_MAX_LINK_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "PCIE_BLK_LOCN": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "PL_LINK_CAP_MAX_LINK_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "PL_LINK_CAP_MAX_LINK_SPEED": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "REF_CLK_FREQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "DRP_CLK_SEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "FREE_RUN_FREQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "CORE_CLK_FREQ": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "PLL_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "USER_CLK_FREQ": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "USER_CLK_FREQ": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "SILICON_REV": [ { "value": "Pre-Production", "resolve_type": "generated", "usage": "all" } ],
         "PIPE_SIM": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
         "VDM_EN": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ],
         "EXT_CH_GT_DRP": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
         "PCIE3_DRP": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
-        "DEDICATE_PERST": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ],
+        "DEDICATE_PERST": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
         "SYS_RESET_POLARITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "MCAP_ENABLEMENT": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
         "EXT_STARTUP_PRIMITIVE": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
         "PF0_VENDOR_ID": [ { "value": "0x10EE", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "PF0_DEVICE_ID": [ { "value": "0x9038", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "PF0_DEVICE_ID": [ { "value": "0x903F", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "PF0_REVISION_ID": [ { "value": "0x00", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "PF0_SUBSYSTEM_VENDOR_ID": [ { "value": "0x10EE", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "PF0_SUBSYSTEM_ID": [ { "value": "0x0007", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
@@ -1022,7 +1022,7 @@
         "EN_TRANSCEIVER_STATUS_PORTS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
         "IS_BOARD_PROJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "EN_GT_SELECTION": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
-        "SELECT_QUAD": [ { "value": "GTH_Quad_224", "resolve_type": "generated", "usage": "all" } ],
+        "SELECT_QUAD": [ { "value": "GTY_Quad_130", "resolve_type": "generated", "usage": "all" } ],
         "ULTRASCALE": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
         "ULTRASCALE_PLUS": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ],
         "VERSAL": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
@@ -1042,7 +1042,7 @@
         "EGW_IS_PARENT_IP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_M_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXIBAR_NUM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "XDMA_NUM_PCIE_TAG": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "EN_AXI_MASTER_IF": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ],
         "EN_WCHNL_0": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ],
@@ -1117,16 +1117,16 @@
         "C_INCLUDE_BAROFFSET_REG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_BASEADDR": [ { "value": "0x83000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_HIGHADDR": [ { "value": "0x83FFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S_AXI_NUM_READ": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_M_AXI_NUM_READ": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_M_AXI_NUM_READQ": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S_AXI_NUM_WRITE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_M_AXI_NUM_WRITE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXI_NUM_WRITE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_M_AXI_NUM_WRITE_SCALE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "MSIX_IMPL_EXT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
         "AXI_ACLK_LOOPBACK": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
-        "PF0_BAR0_APERTURE_SIZE": [ { "value": "0x12", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "PF0_BAR0_APERTURE_SIZE": [ { "value": "0x0E", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "PF0_BAR0_CONTROL": [ { "value": "0x4", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "PF0_BAR1_APERTURE_SIZE": [ { "value": "0x05", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "PF0_BAR1_CONTROL": [ { "value": "0x0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
@@ -1276,11 +1276,11 @@
         "ERRC_DEC_EN": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -1308,10 +1308,10 @@
         "sys_rst_n": [ { "direction": "in", "driver_value": "1" } ],
         "cfg_ltssm_state": [ { "direction": "out", "size_left": "5", "size_right": "0" } ],
         "user_lnk_up": [ { "direction": "out" } ],
-        "pci_exp_txp": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
-        "pci_exp_txn": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
-        "pci_exp_rxp": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
-        "pci_exp_rxn": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "pci_exp_txp": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
+        "pci_exp_txn": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
+        "pci_exp_rxp": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "pci_exp_rxn": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
         "axi_aclk": [ { "direction": "out" } ],
         "axi_aresetn": [ { "direction": "out" } ],
         "axi_ctl_aresetn": [ { "direction": "out" } ],
@@ -1329,8 +1329,8 @@
         "m_axib_awready": [ { "direction": "in", "driver_value": "0" } ],
         "m_axib_awlock": [ { "direction": "out" } ],
         "m_axib_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
-        "m_axib_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
-        "m_axib_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "m_axib_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
+        "m_axib_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
         "m_axib_wlast": [ { "direction": "out" } ],
         "m_axib_wvalid": [ { "direction": "out" } ],
         "m_axib_wready": [ { "direction": "in", "driver_value": "0" } ],
@@ -1349,7 +1349,7 @@
         "m_axib_arlock": [ { "direction": "out" } ],
         "m_axib_arcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
         "m_axib_rid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
-        "m_axib_rdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0" } ],
+        "m_axib_rdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0" } ],
         "m_axib_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
         "m_axib_rlast": [ { "direction": "in", "driver_value": "0" } ],
         "m_axib_rvalid": [ { "direction": "in", "driver_value": "0" } ],
@@ -1374,19 +1374,19 @@
         "s_axil_rvalid": [ { "direction": "out" } ],
         "s_axil_rready": [ { "direction": "in", "driver_value": "0" } ],
         "interrupt_out": [ { "direction": "out" } ],
-        "s_axib_awid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "s_axib_awid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
         "s_axib_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
         "s_axib_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
         "s_axib_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
         "s_axib_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
         "s_axib_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
         "s_axib_awvalid": [ { "direction": "in", "driver_value": "0" } ],
-        "s_axib_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0" } ],
-        "s_axib_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axib_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0" } ],
+        "s_axib_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
         "s_axib_wlast": [ { "direction": "in", "driver_value": "0" } ],
         "s_axib_wvalid": [ { "direction": "in", "driver_value": "0" } ],
         "s_axib_bready": [ { "direction": "in", "driver_value": "0" } ],
-        "s_axib_arid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "s_axib_arid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
         "s_axib_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
         "s_axib_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
         "s_axib_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
@@ -1396,12 +1396,12 @@
         "s_axib_rready": [ { "direction": "in", "driver_value": "0" } ],
         "s_axib_awready": [ { "direction": "out" } ],
         "s_axib_wready": [ { "direction": "out" } ],
-        "s_axib_bid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
+        "s_axib_bid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
         "s_axib_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
         "s_axib_bvalid": [ { "direction": "out" } ],
         "s_axib_arready": [ { "direction": "out" } ],
-        "s_axib_rid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
-        "s_axib_rdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
+        "s_axib_rid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axib_rdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
         "s_axib_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
         "s_axib_rlast": [ { "direction": "out" } ],
         "s_axib_rvalid": [ { "direction": "out" } ]
@@ -1412,7 +1412,7 @@
           "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
           "mode": "slave",
           "parameters": {
-            "FREQ_HZ": [ { "value": "100000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
             "CLK_DOMAIN": [ { "value": "design_1_util_ds_buf_0_0_IBUF_DS_ODIV2", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1480,7 +1480,7 @@
           "parameters": {
             "BOARD.ASSOCIATED_PARAM": [ { "value": "SYS_RST_N_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
             "TYPE": [ { "value": "PCIE_PERST", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
-            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
@@ -1529,10 +1529,10 @@
             "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
             "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-            "DATA_WIDTH": [ { "value": "256", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "512", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "FREQ_HZ": [ { "value": "250000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "2", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1540,7 +1540,7 @@
             "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1599,14 +1599,14 @@
           "address_space_ref": "M_AXI_B",
           "parameters": {
             "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-            "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
             "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
             "NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
             "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-            "DATA_WIDTH": [ { "value": "256", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "512", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "FREQ_HZ": [ { "value": "250000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ID_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1679,7 +1679,7 @@
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
             "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "FREQ_HZ": [ { "value": "250000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "250000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],

project_1.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci

@@ -17,11 +17,11 @@
         "CONST_VAL": [ { "value": "0x1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui

@@ -1,95 +1,210 @@
 {
    "ActiveEmotionalView":"Default View",
-   "Default View_ScaleFactor":"1.10748",
-   "Default View_TopLeft":"777,944",
+   "Default View_ScaleFactor":"0.456305",
+   "Default View_TopLeft":"-1729,-228",
    "ExpandedHierarchyInLayout":"",
    "guistr":"# # String gsaved with Nlview 7.0r4  2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
 #  -string -flagsOSRD
-preplace port UART_0 -pg 1 -lvl 7 -x 2500 -y 470 -defaultsOSRD
-preplace port axil_descriptors -pg 1 -lvl 7 -x 2500 -y 1550 -defaultsOSRD
-preplace port axil_dma_ctrl0 -pg 1 -lvl 7 -x 2500 -y 1580 -defaultsOSRD
-preplace port axil_dma_ctrl1 -pg 1 -lvl 7 -x 2500 -y 1610 -defaultsOSRD
-preplace port axil_util -pg 1 -lvl 7 -x 2500 -y 1640 -defaultsOSRD
-preplace port pcie_mgt_0 -pg 1 -lvl 7 -x 2500 -y 1100 -defaultsOSRD
-preplace port pcie_refclk -pg 1 -lvl 0 -x -30 -y 1350 -defaultsOSRD
-preplace port sys_clk -pg 1 -lvl 0 -x -30 -y 800 -defaultsOSRD
-preplace port axil_timing -pg 1 -lvl 7 -x 2500 -y 1670 -defaultsOSRD
-preplace port axil_data_gen -pg 1 -lvl 7 -x 2500 -y 1700 -defaultsOSRD
-preplace port pcie_m_axi0 -pg 1 -lvl 0 -x -30 -y 1030 -defaultsOSRD
-preplace port pcie_m_axi1 -pg 1 -lvl 0 -x -30 -y 1060 -defaultsOSRD
-preplace port port-id_axi_pcie_aresetn -pg 1 -lvl 7 -x 2500 -y 1190 -defaultsOSRD
-preplace port port-id_axi_pcie_clk -pg 1 -lvl 7 -x 2500 -y 1880 -defaultsOSRD
-preplace port port-id_axil_clk -pg 1 -lvl 7 -x 2500 -y 790 -defaultsOSRD
-preplace port port-id_pcie_rstn -pg 1 -lvl 0 -x -30 -y 1400 -defaultsOSRD
-preplace port port-id_pcie_user_lnk_up -pg 1 -lvl 7 -x 2500 -y 1160 -defaultsOSRD
-preplace portBus axil_resetn -pg 1 -lvl 7 -x 2500 -y 820 -defaultsOSRD
-preplace portBus pcie_cfg_ltssm_state -pg 1 -lvl 7 -x 2500 -y 1130 -defaultsOSRD
-preplace portBus usr_irq_req -pg 1 -lvl 0 -x -30 -y 1430 -defaultsOSRD
-preplace inst axi_interconnect_0 -pg 1 -lvl 5 -x 1560 -y 320 -defaultsOSRD
-preplace inst axi_timer_0 -pg 1 -lvl 6 -x 2140 -y 290 -defaultsOSRD
-preplace inst axi_uartlite_0 -pg 1 -lvl 6 -x 2140 -y 480 -defaultsOSRD
-preplace inst clk_wiz_1 -pg 1 -lvl 5 -x 1560 -y 800 -defaultsOSRD
-preplace inst mdm_1 -pg 1 -lvl 3 -x 710 -y 870 -defaultsOSRD
-preplace inst microblaze_0 -pg 1 -lvl 4 -x 1100 -y 660 -defaultsOSRD
-preplace inst microblaze_0_axi_intc -pg 1 -lvl 3 -x 710 -y 640 -defaultsOSRD
-preplace inst microblaze_0_axi_periph -pg 1 -lvl 6 -x 2140 -y 1610 -defaultsOSRD
-preplace inst microblaze_0_local_memory -pg 1 -lvl 5 -x 1560 -y 670 -defaultsOSRD
-preplace inst microblaze_0_xlconcat -pg 1 -lvl 2 -x 370 -y 720 -defaultsOSRD
-preplace inst rst_clk_wiz_1_100M -pg 1 -lvl 2 -x 370 -y 920 -defaultsOSRD
-preplace inst system_management_wiz_0 -pg 1 -lvl 6 -x 2140 -y 680 -defaultsOSRD
-preplace inst util_ds_buf_0 -pg 1 -lvl 4 -x 1100 -y 1350 -defaultsOSRD
-preplace inst xdma_0 -pg 1 -lvl 5 -x 1560 -y 1440 -defaultsOSRD
-preplace inst xlconstant_0 -pg 1 -lvl 1 -x 70 -y 900 -defaultsOSRD
-preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 6 -x 2140 -y 100 -defaultsOSRD
-preplace inst axi_interconnect_1 -pg 1 -lvl 4 -x 1100 -y 1130 -defaultsOSRD
-preplace netloc S01_ARESETN_1 1 3 4 860 1280 1370J 1270 1720 1300 2480J
-preplace netloc axi_timer_0_interrupt 1 1 6 160 500 NJ 500 NJ 500 1360J 520 1790J 560 2480
-preplace netloc axi_uartlite_0_interrupt 1 1 6 150 100 NJ 100 NJ 100 NJ 100 1810J 400 2450
-preplace netloc clk_wiz_1_locked 1 1 5 170 810 580J 780 NJ 780 1360J 870 1740
-preplace netloc mdm_1_debug_sys_rst 1 1 3 190 820 590J 790 830
-preplace netloc microblaze_0_Clk 1 1 6 180 640 580 530 850 560 1390 110 1800 790 NJ
-preplace netloc microblaze_0_intr 1 2 1 550 650n
-preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 2 3 550 940 840J 570 1360J
-preplace netloc rst_clk_wiz_1_100M_mb_reset 1 2 2 570 520 860J
-preplace netloc rst_clk_wiz_1_100M_peripheral_aresetn 1 2 5 560 460 NJ 460 1360 120 1780 820 NJ
-preplace netloc sys_rst_n_0_1 1 0 5 NJ 1400 NJ 1400 NJ 1400 830J 1470 NJ
-preplace netloc system_management_wiz_0_ip2intc_irpt 1 1 6 170 510 NJ 510 870J 530 NJ 530 1720J 570 2450
-preplace netloc usr_irq_req_0_1 1 0 5 NJ 1430 NJ 1430 NJ 1430 NJ 1430 1330J
-preplace netloc util_ds_buf_0_IBUF_DS_ODIV2 1 4 1 1340 1360n
-preplace netloc util_ds_buf_0_IBUF_OUT 1 4 1 1350 1340n
-preplace netloc xdma_0_axi_aclk 1 3 4 840 1420 1380J 1280 1740 1880 NJ
-preplace netloc xdma_0_axi_ctl_aresetn 1 5 1 1820 1460n
-preplace netloc xdma_0_cfg_ltssm_state 1 5 2 1790J 1280 2460J
-preplace netloc xdma_0_user_lnk_up 1 5 2 1730J 1290 2470J
-preplace netloc xlconstant_0_dout 1 1 1 150 900n
-preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 5 2 1820 10 2480
-preplace netloc CLK_IN1_D_0_1 1 0 5 NJ 800 NJ 800 NJ 800 NJ 800 NJ
-preplace netloc CLK_IN_D_0_1 1 0 4 NJ 1350 NJ 1350 NJ 1350 NJ
-preplace netloc S00_AXI_0_1 1 0 4 NJ 1030 NJ 1030 NJ 1030 850J
-preplace netloc S00_AXI_1 1 4 1 1340 180n
-preplace netloc S01_AXI_0_1 1 0 4 NJ 1060 NJ 1060 NJ 1060 NJ
-preplace netloc axi_interconnect_0_M00_AXI 1 2 4 590 90 NJ 90 NJ 90 1740
-preplace netloc axi_interconnect_0_M01_AXI 1 5 1 1770 240n
-preplace netloc axi_interconnect_0_M02_AXI 1 5 1 1790 320n
-preplace netloc axi_interconnect_0_M03_AXI 1 5 1 1740 340n
-preplace netloc axi_interconnect_0_M04_AXI 1 5 1 1770 360n
-preplace netloc axi_interconnect_1_M00_AXI 1 4 1 1360 1130n
-preplace netloc axi_uartlite_0_UART 1 6 1 NJ 470
-preplace netloc microblaze_0_axi_periph_M00_AXI 1 4 3 1390 1260 NJ 1260 2440
-preplace netloc microblaze_0_axi_periph_M01_AXI 1 6 1 2470J 1550n
-preplace netloc microblaze_0_axi_periph_M02_AXI 1 6 1 2460J 1580n
-preplace netloc microblaze_0_axi_periph_M03_AXI 1 6 1 NJ 1610
-preplace netloc microblaze_0_axi_periph_M04_AXI 1 6 1 2460J 1630n
-preplace netloc microblaze_0_axi_periph_M05_AXI 1 6 1 2470J 1650n
-preplace netloc microblaze_0_axi_periph_M06_AXI 1 6 1 2450J 1670n
-preplace netloc microblaze_0_debug 1 3 1 870 650n
-preplace netloc microblaze_0_dlmb_1 1 4 1 N 640
-preplace netloc microblaze_0_ilmb_1 1 4 1 N 660
-preplace netloc microblaze_0_interrupt 1 3 1 830 630n
-preplace netloc xdma_0_M_AXI_B 1 5 1 1750 1340n
-preplace netloc xdma_0_pcie_mgt 1 5 2 1760J 1270 2450J
-levelinfo -pg 1 -30 70 370 710 1100 1560 2140 2500
-pagesize -pg 1 -db -bbox -sgen -190 0 2720 1970
+preplace port axil_descriptors -pg 1 -lvl 7 -x 5210 -y 980 -defaultsOSRD
+preplace port axil_dma_ctrl0 -pg 1 -lvl 7 -x 5210 -y 1010 -defaultsOSRD
+preplace port axil_dma_ctrl1 -pg 1 -lvl 7 -x 5210 -y 1040 -defaultsOSRD
+preplace port axil_util -pg 1 -lvl 7 -x 5210 -y 1070 -defaultsOSRD
+preplace port pcie_mgt_0 -pg 1 -lvl 7 -x 5210 -y 790 -defaultsOSRD
+preplace port pcie_refclk -pg 1 -lvl 0 -x 0 -y 1120 -defaultsOSRD
+preplace port sys_clk -pg 1 -lvl 0 -x 0 -y 1230 -defaultsOSRD
+preplace port axil_timing -pg 1 -lvl 7 -x 5210 -y 1200 -defaultsOSRD
+preplace port axil_data_gen -pg 1 -lvl 7 -x 5210 -y 1100 -defaultsOSRD
+preplace port pcie_m_axi0 -pg 1 -lvl 0 -x 0 -y 660 -defaultsOSRD
+preplace port pcie_m_axi1 -pg 1 -lvl 0 -x 0 -y 690 -defaultsOSRD
+preplace port pcie_m_axi2 -pg 1 -lvl 0 -x 0 -y 720 -defaultsOSRD
+preplace port pcie_m_axi3 -pg 1 -lvl 0 -x 0 -y 750 -defaultsOSRD
+preplace port axil_dma_ctrl2 -pg 1 -lvl 7 -x 5210 -y 1130 -defaultsOSRD
+preplace port axil_dma_ctrl3 -pg 1 -lvl 7 -x 5210 -y 1160 -defaultsOSRD
+preplace port port-id_axi_pcie_aresetn -pg 1 -lvl 7 -x 5210 -y 1350 -defaultsOSRD
+preplace port port-id_axi_pcie_clk -pg 1 -lvl 7 -x 5210 -y 1380 -defaultsOSRD
+preplace port port-id_axil_clk -pg 1 -lvl 7 -x 5210 -y 590 -defaultsOSRD
+preplace port port-id_pcie_rstn -pg 1 -lvl 0 -x 0 -y 1170 -defaultsOSRD
+preplace port port-id_pcie_user_lnk_up -pg 1 -lvl 7 -x 5210 -y 850 -defaultsOSRD
+preplace portBus axil_resetn -pg 1 -lvl 7 -x 5210 -y 620 -defaultsOSRD
+preplace portBus pcie_cfg_ltssm_state -pg 1 -lvl 7 -x 5210 -y 820 -defaultsOSRD
+preplace portBus usr_irq_req -pg 1 -lvl 0 -x 0 -y 1200 -defaultsOSRD
+preplace inst microblaze_0_local_memory -pg 1 -lvl 5 -x 1800 -y 1054 -defaultsOSRD
+preplace inst axi_interconnect_0 -pg 1 -lvl 5 -x 1800 -y 222 -defaultsOSRD
+preplace inst axi_interconnect_1 -pg 1 -lvl 4 -x 1180 -y 820 -defaultsOSRD
+preplace inst axi_timer_0 -pg 1 -lvl 6 -x 3270 -y 250 -defaultsOSRD
+preplace inst clk_wiz_1 -pg 1 -lvl 5 -x 1800 -y 1774 -defaultsOSRD
+preplace inst mdm_1 -pg 1 -lvl 3 -x 780 -y 490 -defaultsOSRD
+preplace inst microblaze_0 -pg 1 -lvl 4 -x 1180 -y 500 -defaultsOSRD
+preplace inst microblaze_0_axi_intc -pg 1 -lvl 3 -x 780 -y 290 -defaultsOSRD
+preplace inst microblaze_0_axi_periph -pg 1 -lvl 6 -x 3270 -y 1092 -defaultsOSRD
+preplace inst microblaze_0_xlconcat -pg 1 -lvl 2 -x 400 -y 300 -defaultsOSRD
+preplace inst rst_clk_wiz_1_100M -pg 1 -lvl 2 -x 400 -y 560 -defaultsOSRD
+preplace inst system_management_wiz_0 -pg 1 -lvl 6 -x 3270 -y 480 -defaultsOSRD
+preplace inst util_ds_buf_0 -pg 1 -lvl 4 -x 1180 -y 1120 -defaultsOSRD
+preplace inst xdma_0 -pg 1 -lvl 5 -x 1800 -y 1414 -defaultsOSRD
+preplace inst xlconstant_0 -pg 1 -lvl 1 -x 100 -y 540 -defaultsOSRD
+preplace inst axi_interconnect_0|xbar -pg 1 -lvl 2 -x 2200 -y 452 -defaultsOSRD
+preplace inst axi_interconnect_0|s00_couplers -pg 1 -lvl 1 -x 1900 -y 472 -defaultsOSRD
+preplace inst axi_interconnect_0|m00_couplers -pg 1 -lvl 3 -x 2560 -y 152 -defaultsOSRD
+preplace inst axi_interconnect_0|m01_couplers -pg 1 -lvl 3 -x 2560 -y 322 -defaultsOSRD
+preplace inst axi_interconnect_0|m02_couplers -pg 1 -lvl 3 -x 2560 -y 492 -defaultsOSRD
+preplace inst axi_interconnect_0|m03_couplers -pg 1 -lvl 3 -x 2560 -y 662 -defaultsOSRD
+preplace inst axi_interconnect_0|m04_couplers -pg 1 -lvl 3 -x 2560 -y 842 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|xbar -pg 1 -lvl 2 -x 4340 -y 1552 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|s00_couplers -pg 1 -lvl 1 -x 3430 -y 1192 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|s01_couplers -pg 1 -lvl 1 -x 3430 -y 1454 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|m00_couplers -pg 1 -lvl 3 -x 4820 -y 910 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|m01_couplers -pg 1 -lvl 3 -x 4820 -y 1082 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|m02_couplers -pg 1 -lvl 3 -x 4820 -y 1252 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|m03_couplers -pg 1 -lvl 3 -x 4820 -y 1422 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|m04_couplers -pg 1 -lvl 3 -x 4820 -y 1592 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|m05_couplers -pg 1 -lvl 3 -x 4820 -y 1762 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|m06_couplers -pg 1 -lvl 3 -x 4820 -y 2122 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|m07_couplers -pg 1 -lvl 3 -x 4820 -y 1942 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|m08_couplers -pg 1 -lvl 3 -x 4820 -y 2302 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|s00_couplers|auto_cc -pg 1 -lvl 1 -x 3550 -y 1222 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|s01_couplers|auto_ds -pg 1 -lvl 1 -x 3550 -y 1464 -defaultsOSRD
+preplace inst microblaze_0_axi_periph|s01_couplers|auto_pc -pg 1 -lvl 2 -x 3870 -y 1484 -defaultsOSRD
+preplace netloc S01_ARESETN_1 1 3 4 940 1040 1470J 1164 2940 2422 5180J
+preplace netloc axi_timer_0_interrupt 1 1 6 190 1190 NJ 1190 NJ 1190 1510J 1184 2840J 732 5100
+preplace netloc clk_wiz_1_locked 1 1 5 220 1030 NJ 1030 NJ 1030 1480J 1174 2830
+preplace netloc mdm_1_debug_sys_rst 1 1 3 220 460 610J 570 920
+preplace netloc microblaze_0_Clk 1 1 6 210 450 600 590 930 590 1520 1144 2860 590 NJ
+preplace netloc microblaze_0_intr 1 2 1 N 300
+preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 2 3 590J 600 NJ 600 1500
+preplace netloc rst_clk_wiz_1_100M_mb_reset 1 2 2 620 580 940
+preplace netloc rst_clk_wiz_1_100M_peripheral_aresetn 1 2 5 580 610 NJ 610 1540 1134 2920 620 NJ
+preplace netloc sys_rst_n_0_1 1 0 5 NJ 1170 NJ 1170 NJ 1170 930J 1220 1420J
+preplace netloc system_management_wiz_0_ip2intc_irpt 1 1 6 200 1200 NJ 1200 NJ 1200 1520J 1194 2850J 742 5090
+preplace netloc usr_irq_req_0_1 1 0 5 NJ 1200 180J 1210 NJ 1210 NJ 1210 1430J
+preplace netloc util_ds_buf_0_IBUF_DS_ODIV2 1 4 1 1440 1130n
+preplace netloc util_ds_buf_0_IBUF_OUT 1 4 1 1450 1110n
+preplace netloc xdma_0_axi_aclk 1 3 4 920 1050 1460J 1154 2930 2432 5190J
+preplace netloc xdma_0_axi_ctl_aresetn 1 5 1 2950 1162n
+preplace netloc xdma_0_cfg_ltssm_state 1 5 2 2880J 2442 5130J
+preplace netloc xdma_0_user_lnk_up 1 5 2 2890J 752 5110J
+preplace netloc xlconstant_0_dout 1 1 1 180 540n
+preplace netloc CLK_IN1_D_0_1 1 0 5 NJ 1230 NJ 1230 NJ 1230 NJ 1230 1410J
+preplace netloc CLK_IN_D_0_1 1 0 4 NJ 1120 NJ 1120 NJ 1120 NJ
+preplace netloc S00_AXI_0_1 1 0 4 NJ 660 NJ 660 NJ 660 930J
+preplace netloc S00_AXI_1 1 4 1 1500 432n
+preplace netloc S01_AXI_0_1 1 0 4 NJ 690 NJ 690 NJ 690 NJ
+preplace netloc axi_interconnect_0_M00_AXI 1 2 4 580 12 NJ 12 NJ 12 2860
+preplace netloc axi_interconnect_0_M01_AXI 1 5 1 2840 200n
+preplace netloc axi_interconnect_0_M02_AXI 1 2 4 630 22 NJ 22 NJ 22 2830
+preplace netloc axi_interconnect_0_M03_AXI 1 5 1 2840 450n
+preplace netloc axi_interconnect_0_M04_AXI 1 5 1 2880 802n
+preplace netloc axi_interconnect_1_M00_AXI 1 4 1 1490 820n
+preplace netloc microblaze_0_axi_periph_M00_AXI 1 4 3 1540 1204 2870J 762 5090
+preplace netloc microblaze_0_axi_periph_M01_AXI 1 6 1 5090J 980n
+preplace netloc microblaze_0_axi_periph_M02_AXI 1 6 1 5100J 1010n
+preplace netloc microblaze_0_axi_periph_M03_AXI 1 6 1 5110J 1040n
+preplace netloc microblaze_0_axi_periph_M04_AXI 1 6 1 5120J 1070n
+preplace netloc microblaze_0_axi_periph_M05_AXI 1 6 1 5160J 1200n
+preplace netloc microblaze_0_axi_periph_M06_AXI 1 6 1 5140J 1100n
+preplace netloc microblaze_0_debug 1 3 1 920 470n
+preplace netloc microblaze_0_dlmb_1 1 4 1 1530 480n
+preplace netloc microblaze_0_ilmb_1 1 4 1 1510 500n
+preplace netloc microblaze_0_interrupt 1 3 1 940 290n
+preplace netloc xdma_0_M_AXI_B 1 5 1 2910 1122n
+preplace netloc xdma_0_pcie_mgt 1 5 2 2900J 772 5100J
+preplace netloc S02_AXI_0_1 1 0 4 20J 710 NJ 710 NJ 710 NJ
+preplace netloc S03_AXI_0_1 1 0 4 20J 730 NJ 730 NJ 730 NJ
+preplace netloc microblaze_0_axi_periph_M07_AXI 1 6 1 5150 1130n
+preplace netloc microblaze_0_axi_periph_M08_AXI 1 6 1 5170 1160n
+preplace netloc axi_interconnect_0|axi_interconnect_0_ACLK_net 1 0 3 1710 352 2050 352 2370
+preplace netloc axi_interconnect_0|axi_interconnect_0_ARESETN_net 1 0 3 1720 362 2060 342 2360
+preplace netloc axi_interconnect_0|axi_interconnect_0_to_s00_couplers 1 0 1 N 432
+preplace netloc axi_interconnect_0|s00_couplers_to_xbar 1 1 1 N 432
+preplace netloc axi_interconnect_0|m00_couplers_to_axi_interconnect_0 1 3 1 N 152
+preplace netloc axi_interconnect_0|xbar_to_m00_couplers 1 2 1 2340 112n
+preplace netloc axi_interconnect_0|m01_couplers_to_axi_interconnect_0 1 3 1 N 322
+preplace netloc axi_interconnect_0|xbar_to_m01_couplers 1 2 1 2380 282n
+preplace netloc axi_interconnect_0|m02_couplers_to_axi_interconnect_0 1 3 1 N 492
+preplace netloc axi_interconnect_0|xbar_to_m02_couplers 1 2 1 N 452
+preplace netloc axi_interconnect_0|m03_couplers_to_axi_interconnect_0 1 3 1 N 662
+preplace netloc axi_interconnect_0|xbar_to_m03_couplers 1 2 1 2350 472n
+preplace netloc axi_interconnect_0|m04_couplers_to_axi_interconnect_0 1 3 1 N 802
+preplace netloc axi_interconnect_0|xbar_to_m04_couplers 1 2 1 2340 492n
+preplace netloc microblaze_0_axi_periph|microblaze_0_axi_periph_ACLK_net 1 0 3 3240 1082 4160 1082 4580
+preplace netloc microblaze_0_axi_periph|microblaze_0_axi_periph_ARESETN_net 1 0 3 3250 1092 4140 1092 4590
+preplace netloc microblaze_0_axi_periph|S00_ACLK_1 1 0 1 3220 1182n
+preplace netloc microblaze_0_axi_periph|S00_ARESETN_1 1 0 1 3180 1202n
+preplace netloc microblaze_0_axi_periph|S01_ACLK_1 1 0 1 3150 1222n
+preplace netloc microblaze_0_axi_periph|S01_ARESETN_1 1 0 1 3120 1242n
+preplace netloc microblaze_0_axi_periph|M00_ACLK_1 1 0 3 3100J 1012 NJ 1012 4480
+preplace netloc microblaze_0_axi_periph|M00_ARESETN_1 1 0 3 3110J 1022 NJ 1022 4490
+preplace netloc microblaze_0_axi_periph|M01_ACLK_1 1 0 3 3130J 1052 NJ 1052 4610
+preplace netloc microblaze_0_axi_periph|M01_ARESETN_1 1 0 3 3160J 1062 NJ 1062 4600
+preplace netloc microblaze_0_axi_periph|M02_ACLK_1 1 0 3 NJ 1342 NJ 1342 4510
+preplace netloc microblaze_0_axi_periph|M02_ARESETN_1 1 0 3 3200J 1354 NJ 1354 4530
+preplace netloc microblaze_0_axi_periph|M03_ACLK_1 1 0 3 3140J 1032 NJ 1032 4620
+preplace netloc microblaze_0_axi_periph|M03_ARESETN_1 1 0 3 3170J 1042 NJ 1042 4490
+preplace netloc microblaze_0_axi_periph|M04_ACLK_1 1 0 3 3100J 1584 4130J 1412 4560
+preplace netloc microblaze_0_axi_periph|M04_ARESETN_1 1 0 3 3190J 1072 NJ 1072 4570
+preplace netloc microblaze_0_axi_periph|M05_ACLK_1 1 0 3 NJ 1786 NJ 1786 4520
+preplace netloc microblaze_0_axi_periph|M05_ARESETN_1 1 0 3 NJ 1812 NJ 1812 4620
+preplace netloc microblaze_0_axi_periph|M06_ACLK_1 1 0 3 3110J 2052 NJ 2052 4500
+preplace netloc microblaze_0_axi_periph|M06_ARESETN_1 1 0 3 NJ 2062 NJ 2062 4480
+preplace netloc microblaze_0_axi_periph|M07_ACLK_1 1 0 3 3170J 2032 NJ 2032 4610
+preplace netloc microblaze_0_axi_periph|M07_ARESETN_1 1 0 3 3240J 2042 NJ 2042 4620
+preplace netloc microblaze_0_axi_periph|M08_ACLK_1 1 0 3 NJ 2316 NJ 2316 4490
+preplace netloc microblaze_0_axi_periph|M08_ARESETN_1 1 0 3 NJ 2342 NJ 2342 4530
+preplace netloc microblaze_0_axi_periph|microblaze_0_axi_periph_to_s00_couplers 1 0 1 3230 1102n
+preplace netloc microblaze_0_axi_periph|s00_couplers_to_xbar 1 1 1 4150 1222n
+preplace netloc microblaze_0_axi_periph|microblaze_0_axi_periph_to_s01_couplers 1 0 1 3210 1122n
+preplace netloc microblaze_0_axi_periph|s01_couplers_to_xbar 1 1 1 4120 1484n
+preplace netloc microblaze_0_axi_periph|m00_couplers_to_microblaze_0_axi_periph 1 3 1 N 910
+preplace netloc microblaze_0_axi_periph|xbar_to_m00_couplers 1 2 1 4500 870n
+preplace netloc microblaze_0_axi_periph|m01_couplers_to_microblaze_0_axi_periph 1 3 1 N 1082
+preplace netloc microblaze_0_axi_periph|xbar_to_m01_couplers 1 2 1 4520 1042n
+preplace netloc microblaze_0_axi_periph|m02_couplers_to_microblaze_0_axi_periph 1 3 1 N 1252
+preplace netloc microblaze_0_axi_periph|xbar_to_m02_couplers 1 2 1 4540 1212n
+preplace netloc microblaze_0_axi_periph|m03_couplers_to_microblaze_0_axi_periph 1 3 1 N 1422
+preplace netloc microblaze_0_axi_periph|xbar_to_m03_couplers 1 2 1 4550 1382n
+preplace netloc microblaze_0_axi_periph|m04_couplers_to_microblaze_0_axi_periph 1 3 1 N 1592
+preplace netloc microblaze_0_axi_periph|xbar_to_m04_couplers 1 2 1 N 1552
+preplace netloc microblaze_0_axi_periph|m05_couplers_to_microblaze_0_axi_periph 1 3 1 N 1762
+preplace netloc microblaze_0_axi_periph|xbar_to_m05_couplers 1 2 1 4530 1572n
+preplace netloc microblaze_0_axi_periph|m06_couplers_to_microblaze_0_axi_periph 1 3 1 4970 1882n
+preplace netloc microblaze_0_axi_periph|xbar_to_m06_couplers 1 2 1 4510 1592n
+preplace netloc microblaze_0_axi_periph|m07_couplers_to_microblaze_0_axi_periph 1 3 1 N 1902
+preplace netloc microblaze_0_axi_periph|xbar_to_m07_couplers 1 2 1 4500 1612n
+preplace netloc microblaze_0_axi_periph|m08_couplers_to_microblaze_0_axi_periph 1 3 1 N 2262
+preplace netloc microblaze_0_axi_periph|xbar_to_m08_couplers 1 2 1 4490 1632n
+preplace netloc axi_interconnect_0|s00_couplers|s00_couplers_to_s00_couplers 1 0 1 N 432
+preplace netloc axi_interconnect_0|m04_couplers|m04_couplers_to_m04_couplers 1 0 1 N 802
+preplace netloc microblaze_0_axi_periph|s00_couplers|M_ACLK_1 1 0 1 N 1242
+preplace netloc microblaze_0_axi_periph|s00_couplers|S_ACLK_1 1 0 1 3380 1202n
+preplace netloc microblaze_0_axi_periph|s00_couplers|M_ARESETN_1 1 0 1 N 1262
+preplace netloc microblaze_0_axi_periph|s00_couplers|S_ARESETN_1 1 0 1 3390 1222n
+preplace netloc microblaze_0_axi_periph|s00_couplers|s00_couplers_to_auto_cc 1 0 1 N 1182
+preplace netloc microblaze_0_axi_periph|s00_couplers|auto_cc_to_s00_couplers 1 1 1 N 1222
+preplace netloc microblaze_0_axi_periph|s01_couplers|S_ACLK_1 1 0 2 3380 1544 3710
+preplace netloc microblaze_0_axi_periph|s01_couplers|S_ARESETN_1 1 0 2 3390 1554 3720
+preplace netloc microblaze_0_axi_periph|s01_couplers|s01_couplers_to_auto_ds 1 0 1 N 1444
+preplace netloc microblaze_0_axi_periph|s01_couplers|auto_ds_to_auto_pc 1 1 1 N 1464
+preplace netloc microblaze_0_axi_periph|s01_couplers|auto_pc_to_s01_couplers 1 2 1 N 1484
+preplace netloc microblaze_0_axi_periph|m07_couplers|m07_couplers_to_m07_couplers 1 0 1 N 1902
+preplace netloc microblaze_0_axi_periph|m08_couplers|m08_couplers_to_m08_couplers 1 0 1 N 2262
+levelinfo -pg 1 0 100 400 780 1180 1800 3270 5210
+levelinfo -hier axi_interconnect_0 * 1900 2200 2560 *
+levelinfo -hier microblaze_0_axi_periph * 3430 4340 4820 *
+levelinfo -hier axi_interconnect_0|s00_couplers * *
+levelinfo -hier axi_interconnect_0|m04_couplers * *
+levelinfo -hier microblaze_0_axi_periph|s00_couplers * 3550 *
+levelinfo -hier microblaze_0_axi_periph|s01_couplers * 3550 3870 *
+levelinfo -hier microblaze_0_axi_periph|m07_couplers * *
+levelinfo -hier microblaze_0_axi_periph|m08_couplers * *
+pagesize -pg 1 -db -bbox -sgen -160 0 5430 2460
+pagesize -hier axi_interconnect_0 -db -bbox -sgen 1680 52 2740 932
+pagesize -hier microblaze_0_axi_periph -db -bbox -sgen 3070 802 5000 2392
+pagesize -hier axi_interconnect_0|s00_couplers -db -bbox -sgen 1820 402 1980 542
+pagesize -hier axi_interconnect_0|m04_couplers -db -bbox -sgen 2480 772 2640 912
+pagesize -hier microblaze_0_axi_periph|s00_couplers -db -bbox -sgen 3350 1122 3740 1322
+pagesize -hier microblaze_0_axi_periph|s01_couplers -db -bbox -sgen 3350 1384 4050 1564
+pagesize -hier microblaze_0_axi_periph|m07_couplers -db -bbox -sgen 4740 1872 4900 2012
+pagesize -hier microblaze_0_axi_periph|m08_couplers -db -bbox -sgen 4740 2232 4900 2372
 "
 }
 0

project_1.srcs/sources_1/hdl/dma_engine_256_og.sv

@@ -1,489 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////
-//
-// Author         : Torry Akins
-// Creation Date  : 06/04/2024
-// File Name      : dma_engine_256.sv
-// Tool Version   : 2021.2
-// Description    : DMA Engine (256 bits wide)
-//
-// Copyright (c) 2024 Wide Swath Research, LLC.
-// This design is confidential and is the proprietary property
-// of Wide Swath Research, LLC.
-//
-// Design licensed for use by Aloft Sensing, Inc.
-//
-//////////////////////////////////////////////////////////////////////////////
-
-module dma_engine_256 (
-      axi4l_intf.slave axi,
-      axi4s_intf.slave axis,
-      axi4_intf.master axim
-   );
-   
-   // incoming pipeline of write address
-   reg awaddr_valid;
-   reg [axi.AXI_ADDR_WIDTH-1:0] awaddr;
-
-   // incoming pipeline of write data
-   reg wdata_valid;
-   reg [((axi.AXI_DATA_WIDTH/8)-1):0] wstrb;
-   reg [axi.AXI_DATA_WIDTH-1:0] wdata;
-   
-   // incoming pipeline of read address
-   reg araddr_valid;
-   reg [axi.AXI_ADDR_WIDTH:0] araddr;
-   
-   // outgoing pipeline of read data
-   reg rvalid;
-   reg [axi.AXI_DATA_WIDTH-1:0] rdata;
-      
-   integer byte_index;      
-      
-   reg [axi.AXI_DATA_WIDTH-1:0] ctrl_reg[3:0];
-   wire [axi.AXI_DATA_WIDTH-1:0] status_reg[4:0];
-   
-   reg ctrl_fifo_wren;
-   reg [127:0] ctrl_fifo_din;
-
-   wire dma_rst;
-   wire dma_enable;
-
-   wire ctrl_fifo_rst;
-   reg ctrl_fifo_rden;
-   wire [71:0] ctrl_fifo_dout;
-
-   wire ctrl_fifo_full;
-   wire ctrl_fifo_empty;
-   wire [9:0] ctrl_fifo_count;
-
-   wire stat_fifo_rst;
-
-   reg stat_fifo_wren;
-   reg [71:0] stat_fifo_din;
-   reg stat_fifo_rden;
-   wire [71:0] stat_fifo_dout;
-
-   wire stat_fifo_full;
-   wire stat_fifo_empty;
-   wire [9:0] stat_fifo_count;
-
-   reg [1:0] state;
-
-	reg [71:0] active_buf;
-	reg [22:0] remaining_len;
-	reg [22:0] bytes_written;
-
-   wire s_axis_s2mm_cmd_tvalid;
-   wire s_axis_s2mm_cmd_tready;
-   reg [79:0]  s_axis_s2mm_cmd_tdata;
-
-   wire m_axis_s2mm_sts_tvalid;
-   wire m_axis_s2mm_sts_tready;
-   wire [7:0] m_axis_s2mm_sts_tdata;
-
-
-   // ready while data hasn't been latched and still waiting
-   // for acknowledgement to our response
-   assign axi.awready = !awaddr_valid && !axi.bvalid && axi.resetn;
-   assign axi.wready = !wdata_valid && !axi.bvalid && axi.resetn;
-   
-	always @( posedge axi.clk )
-   begin
-      if ( axi.resetn == 1'b0 ) begin
-         awaddr_valid <= 1'b0; 
-         awaddr <= 'b0; 
-         wdata_valid <= 1'b0;
-         wstrb <= 'b0;
-         wdata <= 'b0;    
-         axi.bvalid <= 1'b0;
-         axi.bresp  <= 2'b0;                       
-	   end
-	   else begin   
-         // latch awaddr and valid signal
-         if (axi.awready && axi.awvalid) begin 
-            awaddr_valid <= 1'b1;   
-            awaddr <= axi.awaddr; 
-         end
-         
-         // latch wirte data and valid signal
-         if (axi.wready && axi.wvalid) begin 
-            wdata_valid <= 1'b1;   
-            wstrb <= axi.wstrb;
-            wdata <= axi.wdata;    
-         end    
-         
-         // clear valids when both high;
-         // data needs to be consumed on this same condition
-         if (awaddr_valid && wdata_valid && !axi.bvalid) begin
-             awaddr_valid <= 1'b0; 
-             wdata_valid <= 1'b0;
-             
-             axi.bvalid <= 1'b1;
-             axi.bresp  <= 2'b0; // 'OKAY' response          
-         end  
-         
-         // clear bvalid when it has been acknowledged
-         if (axi.bvalid && axi.bready) begin
-            axi.bvalid <= 1'b0;
-         end
-      end
-	end
-	
-	// ready while data hasn't been latched and still waiting
-   // for acknowledgement to our response
-	assign axi.arready = !araddr_valid && !axi.rvalid && axi.resetn;
-	   
-	always @( posedge axi.clk )
-   begin
-      if ( axi.resetn == 1'b0 ) begin
-         araddr_valid <= 1'b0; 
-         araddr <= 'b0; 
-         axi.rvalid <= 1'b0;
-         axi.rresp  <= 2'b0;                       
-         axi.rdata <= 'b0;    
-	   end
-	   else begin   
-         // latch araddr and valid signal	   
-         if (axi.arready && axi.arvalid) begin 
-            araddr_valid <= 1'b1;   
-            araddr <= axi.araddr; 
-         end
-                  
-         // if address is valid and rdata has been latched;
-         // set axi bus rdata and valid signal
-         if (araddr_valid && rvalid && !axi.rvalid) begin
-             araddr_valid <= 1'b0; 
-             
-             axi.rvalid <= 1'b1;
-             axi.rresp  <= 2'b0; // 'OKAY' response     
-             axi.rdata <= rdata;     
-         end  
-         
-         // clear rvalid when it has been acknowledged
-         if (axi.rvalid && axi.rready) begin
-            axi.rvalid <= 1'b0;
-         end
-      end
-	end
-	
-	always @( posedge axi.clk )
-   begin
-      if ( axi.resetn == 1'b0 ) begin
-         ctrl_reg[0] <= 'b111;
-         ctrl_reg[1] <= 'b0;
-         ctrl_reg[2] <= 'b0;
-         ctrl_reg[3] <= 'b0;
-
-	      ctrl_fifo_wren <= 'b0;
-	      ctrl_fifo_din <= 'b0;
-	      
-	      stat_fifo_rden <= 1'b0;
-
-         rvalid <= 1'b0;                      
-         rdata <= 'b0; 
-	   end
-	   else begin   
-	   
-	      ctrl_fifo_wren <= 'b0;
-	      // everything is valid;  latch data to the correct location
-         if (awaddr_valid && wdata_valid) begin
-            for ( byte_index = 0; byte_index <= (axi.AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) begin
-               if ( wstrb[byte_index] == 1 ) begin            
-                  if ( awaddr[7:0] == 'h00 ) 
-                     ctrl_reg[0][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
-      
-                  if ( awaddr[7:0] == 'h04 ) 
-                     ctrl_reg[1][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
-      
-                  if ( awaddr[7:0] == 'h08 ) 
-                     ctrl_reg[2][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
-      
-                  if ( awaddr[7:0] == 'h0C ) 
-                     ctrl_reg[3][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
-     
-                  if ( awaddr[7:0] == 'h20 ) 
-                     ctrl_fifo_din[(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
-                     
-                  if ( awaddr[7:0] == 'h24 ) 
-                     ctrl_fifo_din[(byte_index*8)+32 +: 8] <= wdata[(byte_index*8) +: 8];
-                                          
-                  if ( awaddr[7:0] == 'h28 ) begin
-                     ctrl_fifo_din[(byte_index*8)+64 +: 8] <= wdata[(byte_index*8) +: 8]; 
-                     if (byte_index == 0) ctrl_fifo_wren <= 1'b1;
-                  end                    
-               end  
-            end          
-         end  
-         
-         stat_fifo_rden <= 1'b0;
-         
-         // by default rvalid is low; unless read address is valid;
-         // latch appropriate data and set valid signal
-         rvalid <= 1'b0;
-         if (araddr_valid  && !rvalid) begin
-            if ( araddr[7:0] == 'h0 )
-               rdata <= ctrl_reg[0];
-            if ( araddr[7:0] == 'h4 ) 
-               rdata <= ctrl_reg[1];   
-            if ( araddr[7:0] == 'h8 ) 
-               rdata <= ctrl_reg[2]; 
-            if ( araddr[7:0] == 'hC ) 
-               rdata <= ctrl_reg[3];    
-            if ( araddr[7:0] == 'h10 ) 
-               rdata <= status_reg[0];
-            if ( araddr[7:0] == 'h14 ) 
-               rdata <= status_reg[1];   
-            if ( araddr[7:0] == 'h18 ) 
-               rdata <= status_reg[2]; 
-            if ( araddr[7:0] == 'h1C ) 
-               rdata <= status_reg[3];    
-               
-            if ( araddr[7:0] == 'h20 ) 
-               rdata <= stat_fifo_dout[31:0];                                              
-   
-            if ( araddr[7:0] == 'h24 ) begin 
-               rdata <= stat_fifo_dout[63:32];
-            end
-               
-            if ( araddr[7:0] == 'h28 ) begin 
-               rdata <= {24'b0, stat_fifo_dout[71:64]};
-               stat_fifo_rden <= 1'b1;   
-            end
-
-            if ( araddr[7:0] == 'h2C) begin
-               rdata <= status_reg[4];
-            end
-                           
-            rvalid <= 1'b1;
-         end               
-      end
-             
-   end	
-   
-
-      
-   assign ctrl_fifo_rst = ctrl_reg[0][0];
-   assign stat_fifo_rst = ctrl_reg[0][1];
-   assign dma_rst = ctrl_reg[0][2];
-   
-   assign dma_enable = ctrl_reg[0][8];
-  
-   assign status_reg[0] = {30'h00, state};
-   assign status_reg[1] = {16'h00, 8'd23, 8'd9};   
-   assign status_reg[2] = {6'b0, ctrl_fifo_count, 15'b0, ctrl_fifo_full};
-   assign status_reg[3] = {6'b0, stat_fifo_count, 15'b0, stat_fifo_empty};
-   assign status_reg[4] = 32'hBEEF_BEEF;
-
-      
-   // State Machines
-   parameter DMA_IDLE = 0;   
-   parameter DMA_START = 1;   
-   parameter DMA_ACTIVE = 2;   
-   parameter DMA_COMP = 3;   
-
-   axi4s_intf # (
-      .AXI_DATA_WIDTH(axis.AXI_DATA_WIDTH)
-      ) 
-   axis_gated(
-      .clk(axis.clk)
-      );     	
-   
-	always @( posedge axi.clk ) 
-   begin
-      ctrl_fifo_rden <= 1'b0;
-      stat_fifo_wren <= 1'b0;
-      
-      if ( dma_rst == 1'b1 ) begin
-         state <= DMA_IDLE;
-	   end
-	   else begin   
-         case (state) 
-            DMA_IDLE: begin
-               s_axis_s2mm_cmd_tdata <= 'b0;
-               s_axis_s2mm_cmd_tdata[71:32] <= ctrl_fifo_dout[71:32];
-               s_axis_s2mm_cmd_tdata[30] <= 1'b1;              
-               s_axis_s2mm_cmd_tdata[23] <= 1'b1;      
-               s_axis_s2mm_cmd_tdata[22:0] <= ctrl_fifo_dout[31:9];    
-                  
-               active_buf <= ctrl_fifo_dout;
-               remaining_len <= ctrl_fifo_dout[31:9];
-               bytes_written <= 'b0;                  
-                           
-               if ((ctrl_fifo_empty == 1'b0) && ( dma_enable == 1'b1 )) begin
-                  ctrl_fifo_rden <= 1'b1; 
-                  state <= DMA_START;
-               end            
-            end
-            DMA_START : begin
-               if (s_axis_s2mm_cmd_tready == 1'b1) begin      
-                  state  <= DMA_ACTIVE;
-               end
-            end    
-                    
-            DMA_ACTIVE : begin
-               if ((axis_gated.tready == 1'b1) && (axis_gated.tvalid == 1'b1)) begin     
-                  if ( dma_enable == 1'b1 ) begin
-                     remaining_len <= remaining_len - (axis.AXI_DATA_WIDTH/8);
-                     bytes_written <= bytes_written + (axis.AXI_DATA_WIDTH/8);
-                  
-                     if (remaining_len == (axis.AXI_DATA_WIDTH/8))  begin 
-                        state  <= DMA_COMP;
-                     end
-                  end
-                  else begin
-                     state  <= DMA_COMP;
-                  end                  
-               end
-            end            
-
-            DMA_COMP: begin
-               if (m_axis_s2mm_sts_tvalid == 1'b1) begin //TODO: this is a bug
-                  stat_fifo_wren <= 1'b1;
-                  
-                  stat_fifo_din <= active_buf;
-                  stat_fifo_din[31:9] <= bytes_written;    
-                  
-                  state <= DMA_IDLE;                 
-               end   
-            end            
-
-            default : begin
-               state <= DMA_IDLE;
-            end      
-         endcase                      
-      end             
-   end	   
-   
-   assign s_axis_s2mm_cmd_tvalid = (state == DMA_START) ? 1'b1 : 1'b0;
-   
-   assign axis_gated.tdata = axis.tdata;
-   assign axis_gated.tkeep = axis.tkeep;
-   assign axis_gated.tlast = ((remaining_len == (axis.AXI_DATA_WIDTH/8)) || ( dma_enable == 1'b0 )) ? 1'b1 : 1'b0;
-   assign axis_gated.tvalid = (state == DMA_ACTIVE) ? (( dma_enable == 1'b0 ) ? 1'b1 : axis.tvalid) : 1'b0;
-   assign axis.tready = (state == DMA_ACTIVE) ? axis_gated.tready : (( dma_enable == 1'b0 ) ? 1'b1 : 1'b0);
-                                                                           // This can be removed and changed back to just 1'b0;
-   assign m_axis_s2mm_sts_tready = (state == DMA_COMP) ? 1'b1 : 1'b0;  
-      
-   // basic idea behind datamover control;
-   // control fifo allows dma driver to allocate PS DDR buffer and load the physical address 
-   //    into the fifo; once the transfer is complete the result fifo will be loaded with completion result 
-   //    that will also contain the physical DDR buffer address 
-
-   dma_ctrl_status_fifo_0 ctrl_fifo_i (
-      .clk( axi.clk ), // : IN STD_LOGIC;
-      .srst( ctrl_fifo_rst ), // : IN STD_LOGIC;
-      .din( ctrl_fifo_din[71:0] ), // : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
-      .wr_en( ctrl_fifo_wren ), // : IN STD_LOGIC;
-      .rd_en( ctrl_fifo_rden ), // : IN STD_LOGIC;
-      .dout( ctrl_fifo_dout ), // : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
-      .full( ctrl_fifo_full ), // : OUT STD_LOGIC;
-      .empty( ctrl_fifo_empty ), // : OUT STD_LOGIC;
-      .data_count( ctrl_fifo_count ), // : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
-      .wr_rst_busy( ), 
-      .rd_rst_busy( )
-   );
-   
-   dma_ctrl_status_fifo_0 stat_fifo_i (
-      .clk( axi.clk ), // : IN STD_LOGIC;
-      .srst( stat_fifo_rst ), // : IN STD_LOGIC;
-      .din( stat_fifo_din ), // : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
-      .wr_en( stat_fifo_wren ), // : IN STD_LOGIC;
-      .rd_en( stat_fifo_rden ), // : IN STD_LOGIC;
-      .dout( stat_fifo_dout ), // : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
-      .full( stat_fifo_full ), // : OUT STD_LOGIC;
-      .empty( stat_fifo_empty ), // : OUT STD_LOGIC;
-      .data_count( stat_fifo_count ), // : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
-      .wr_rst_busy( ), 
-      .rd_rst_busy( )
-   );   
-    
-    // Do a soft shutdown of the datamover on a reset request.  This should ensure the AXI bus does not get hung mid burst
-    // and allow the datamover to be instantiated without using store-forward.  This will save blockrams, and is OK because we already
-    // have buffering in the receive path
-    logic s2mm_err;
-    logic s2mm_halt;
-    logic s2mm_halt_cmplt;
-    logic datamover_rst;
-    logic dma_rst_q;
-    logic dma_rst_q2;
-    logic dma_rst_red;
-    
-    always @ (posedge axim.clk) begin
-    
-        dma_rst_q <= dma_rst;
-        dma_rst_q2 <= dma_rst_q;
-        dma_rst_red <= dma_rst_q & ~dma_rst_q;
-        
-        
-        s2mm_halt <= dma_rst;
-        
-        // Clear the datamover reset when the dma reset clears
-        if (dma_rst == 1'b0) begin
-            datamover_rst <= 1'b0;
-//            s2mm_halt <= 1'b0;
-        end
-//        else if (dma_rst_red == 1'b1) begin
-//            // Trigger soft shutdown when the dma reset signal goes high
-//            s2mm_halt <= 1;
-//        end
-        else if (s2mm_halt_cmplt == 1'b1) begin
-            // Wait for halt complete to trigger datamover reset
-            datamover_rst <= 1'b1;
-        end
-    
-    end   
-   
-   axi_datamover_256_0 axi_datamover_0_i (
-      .m_axi_s2mm_aclk( axim.clk ), //
-//      .m_axi_s2mm_aresetn( ~dma_rst ), // : IN STD_LOGIC;
-      .m_axi_s2mm_aresetn( ~datamover_rst ), // : IN STD_LOGIC;
-      
-      .s2mm_halt(s2mm_halt),                                    // input wire s2mm_halt
-      .s2mm_halt_cmplt(s2mm_halt_cmplt),                        // output wire s2mm_halt_cmplt
-      
-      .s2mm_allow_addr_req(1'b1),                // input wire s2mm_allow_addr_req
-      .s2mm_addr_req_posted(),              // output wire s2mm_addr_req_posted
-      .s2mm_wr_xfer_cmplt(),                  // output wire s2mm_wr_xfer_cmplt
-      .s2mm_ld_nxt_len(),                        // output wire s2mm_ld_nxt_len
-      .s2mm_wr_len(),                                // output wire [7 : 0] s2mm_wr_len
-      
-      .s2mm_err(s2mm_err), // : OUT STD_LOGIC;
-      
-      .m_axis_s2mm_cmdsts_awclk( axi.clk ), // : IN STD_LOGIC;
-      .m_axis_s2mm_cmdsts_aresetn( ~dma_rst ), // : IN STD_LOGIC;
-      .s_axis_s2mm_cmd_tvalid( s_axis_s2mm_cmd_tvalid ), // : IN STD_LOGIC;
-      .s_axis_s2mm_cmd_tready( s_axis_s2mm_cmd_tready ), // : OUT STD_LOGIC;
-      .s_axis_s2mm_cmd_tdata( s_axis_s2mm_cmd_tdata), // : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
-      .m_axis_s2mm_sts_tvalid( m_axis_s2mm_sts_tvalid ), // : OUT STD_LOGIC;
-      .m_axis_s2mm_sts_tready( m_axis_s2mm_sts_tready), // : IN STD_LOGIC;
-      .m_axis_s2mm_sts_tdata( m_axis_s2mm_sts_tdata ), // : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-      .m_axis_s2mm_sts_tkeep( ), // : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-      .m_axis_s2mm_sts_tlast( ), // : OUT STD_LOGIC;
-      
-      .m_axi_s2mm_awaddr( axim.awaddr ), // : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-      .m_axi_s2mm_awlen( axim.awlen ), // : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-      .m_axi_s2mm_awsize( axim.awsize ), // : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
-      .m_axi_s2mm_awburst( axim.awburst ), // : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-      .m_axi_s2mm_awprot( axim.awprot ), // : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
-      .m_axi_s2mm_awcache( axim.awcache ), // : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-      .m_axi_s2mm_awuser(  ), // : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-      .m_axi_s2mm_awvalid( axim.awvalid ), // : OUT STD_LOGIC;
-      .m_axi_s2mm_awready( axim.awready ), // : IN STD_LOGIC;
-      .m_axi_s2mm_wdata( axim.wdata ), // : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
-      .m_axi_s2mm_wstrb( axim.wstrb ), // : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-      .m_axi_s2mm_wlast( axim.wlast ), // : OUT STD_LOGIC;
-      .m_axi_s2mm_wvalid( axim.wvalid ), // : OUT STD_LOGIC;
-      .m_axi_s2mm_wready( axim.wready ), // : IN STD_LOGIC;
-      .m_axi_s2mm_bresp( axim.bresp ), // : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-      .m_axi_s2mm_bvalid( axim.bvalid ), // : IN STD_LOGIC;
-      .m_axi_s2mm_bready( axim.bready ), // : OUT STD_LOGIC;
-      
-      .s_axis_s2mm_tdata( axis_gated.tdata ), // : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
-      .s_axis_s2mm_tkeep( axis_gated.tkeep ), // : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-      .s_axis_s2mm_tlast( axis_gated.tlast ), // : IN STD_LOGIC;
-      .s_axis_s2mm_tvalid( axis_gated.tvalid ), // : IN STD_LOGIC;
-      .s_axis_s2mm_tready( axis_gated.tready ) // : OUT STD_LOGIC
-   );
-
-endmodule

project_1.srcs/sources_1/hdl/top.sv

@@ -9,10 +9,10 @@ module top #
 (   
     input  wire 		sys_clk_p,
     input  wire 		sys_clk_n,
-    output wire [2:0]   leds,
-    input  wire         uart_rxd,
-    output wire         uart_txd,
-    output wire         fan_pwm,
+    // output wire [2:0]   leds,
+    // input  wire         uart_rxd,
+    // output wire         uart_txd,
+    // output wire         fan_pwm,
 
     output wire [7:0]   pcie_mgt_txp,
     output wire [7:0]   pcie_mgt_txn,
@@ -76,7 +76,7 @@ data_gen_if (
     .resetn(axi_pcie_resetn)
 );
 
-parameter NUM_DMA = 2;
+parameter NUM_DMA = 4;
 
 axi4l_intf # (
     .AXI_ADDR_WIDTH(32), 
@@ -108,8 +108,8 @@ design_1 design_1_i
 (
     .sys_clk_clk_n(sys_clk_n),
     .sys_clk_clk_p(sys_clk_p),
-    .UART_0_rxd(uart_rxd),
-    .UART_0_txd(uart_txd),
+    // .UART_0_rxd(uart_rxd),
+    // .UART_0_txd(uart_txd),
     .pcie_mgt_0_rxn(pcie_mgt_rxn),
     .pcie_mgt_0_rxp(pcie_mgt_rxp),
     .pcie_mgt_0_txn(pcie_mgt_txn),
@@ -246,17 +246,46 @@ design_1 design_1_i
     .axil_dma_ctrl1_wstrb(pcie_dma_ctrl_axi[1].wstrb),
     .axil_dma_ctrl1_wvalid(pcie_dma_ctrl_axi[1].wvalid),
 
-    // .pcie_m_axi0_araddr (pcie_dma_maxi[0].araddr),
-    // .pcie_m_axi0_arburst(pcie_dma_maxi[0].arburst),
-    // .pcie_m_axi0_arcache(pcie_dma_maxi[0].arcache),
-    // .pcie_m_axi0_arid   (0),
-    // .pcie_m_axi0_arlen  (pcie_dma_maxi[0].arlen),
-    // .pcie_m_axi0_arlock (pcie_dma_maxi[0].arlock),
-    // .pcie_m_axi0_arprot (pcie_dma_maxi[0].arprot),
-    // .pcie_m_axi0_arqos  (pcie_dma_maxi[0].arqos),
-    // .pcie_m_axi0_arready(pcie_dma_maxi[0].arready),
-    // .pcie_m_axi0_arsize (pcie_dma_maxi[0].arsize),
-    // .pcie_m_axi0_arvalid(pcie_dma_maxi[0].arvalid),
+    .axil_dma_ctrl2_araddr(pcie_dma_ctrl_axi[2].araddr),
+    .axil_dma_ctrl2_arprot(pcie_dma_ctrl_axi[2].arprot),
+    .axil_dma_ctrl2_arready(pcie_dma_ctrl_axi[2].arready),
+    .axil_dma_ctrl2_arvalid(pcie_dma_ctrl_axi[2].arvalid),
+    .axil_dma_ctrl2_awaddr(pcie_dma_ctrl_axi[2].awaddr),
+    .axil_dma_ctrl2_awprot(pcie_dma_ctrl_axi[2].awprot),
+    .axil_dma_ctrl2_awready(pcie_dma_ctrl_axi[2].awready),
+    .axil_dma_ctrl2_awvalid(pcie_dma_ctrl_axi[2].awvalid),
+    .axil_dma_ctrl2_bready(pcie_dma_ctrl_axi[2].bready),
+    .axil_dma_ctrl2_bresp(pcie_dma_ctrl_axi[2].bresp),
+    .axil_dma_ctrl2_bvalid(pcie_dma_ctrl_axi[2].bvalid),
+    .axil_dma_ctrl2_rdata(pcie_dma_ctrl_axi[2].rdata),
+    .axil_dma_ctrl2_rready(pcie_dma_ctrl_axi[2].rready),
+    .axil_dma_ctrl2_rresp(pcie_dma_ctrl_axi[2].rresp),
+    .axil_dma_ctrl2_rvalid(pcie_dma_ctrl_axi[2].rvalid),
+    .axil_dma_ctrl2_wdata(pcie_dma_ctrl_axi[2].wdata),
+    .axil_dma_ctrl2_wready(pcie_dma_ctrl_axi[2].wready),
+    .axil_dma_ctrl2_wstrb(pcie_dma_ctrl_axi[2].wstrb),
+    .axil_dma_ctrl2_wvalid(pcie_dma_ctrl_axi[2].wvalid),
+    
+    .axil_dma_ctrl3_araddr(pcie_dma_ctrl_axi[3].araddr),
+    .axil_dma_ctrl3_arprot(pcie_dma_ctrl_axi[3].arprot),
+    .axil_dma_ctrl3_arready(pcie_dma_ctrl_axi[3].arready),
+    .axil_dma_ctrl3_arvalid(pcie_dma_ctrl_axi[3].arvalid),
+    .axil_dma_ctrl3_awaddr(pcie_dma_ctrl_axi[3].awaddr),
+    .axil_dma_ctrl3_awprot(pcie_dma_ctrl_axi[3].awprot),
+    .axil_dma_ctrl3_awready(pcie_dma_ctrl_axi[3].awready),
+    .axil_dma_ctrl3_awvalid(pcie_dma_ctrl_axi[3].awvalid),
+    .axil_dma_ctrl3_bready(pcie_dma_ctrl_axi[3].bready),
+    .axil_dma_ctrl3_bresp(pcie_dma_ctrl_axi[3].bresp),
+    .axil_dma_ctrl3_bvalid(pcie_dma_ctrl_axi[3].bvalid),
+    .axil_dma_ctrl3_rdata(pcie_dma_ctrl_axi[3].rdata),
+    .axil_dma_ctrl3_rready(pcie_dma_ctrl_axi[3].rready),
+    .axil_dma_ctrl3_rresp(pcie_dma_ctrl_axi[3].rresp),
+    .axil_dma_ctrl3_rvalid(pcie_dma_ctrl_axi[3].rvalid),
+    .axil_dma_ctrl3_wdata(pcie_dma_ctrl_axi[3].wdata),
+    .axil_dma_ctrl3_wready(pcie_dma_ctrl_axi[3].wready),
+    .axil_dma_ctrl3_wstrb(pcie_dma_ctrl_axi[3].wstrb),
+    .axil_dma_ctrl3_wvalid(pcie_dma_ctrl_axi[3].wvalid),    
+
     .pcie_m_axi0_awaddr (pcie_dma_maxi[0].awaddr),
     .pcie_m_axi0_awburst(pcie_dma_maxi[0].awburst),
     .pcie_m_axi0_awcache(pcie_dma_maxi[0].awcache),
@@ -271,29 +300,12 @@ design_1 design_1_i
     .pcie_m_axi0_bready (pcie_dma_maxi[0].bready),
     .pcie_m_axi0_bresp  (pcie_dma_maxi[0].bresp),
     .pcie_m_axi0_bvalid (pcie_dma_maxi[0].bvalid),
-    // .pcie_m_axi0_rdata  (pcie_dma_maxi[0].rdata),
-    // .pcie_m_axi0_rid    (),
-    // .pcie_m_axi0_rlast  (pcie_dma_maxi[0].rlast),
-    // .pcie_m_axi0_rready (pcie_dma_maxi[0].rready),
-    // .pcie_m_axi0_rresp  (pcie_dma_maxi[0].rresp),
-    // .pcie_m_axi0_rvalid (pcie_dma_maxi[0].rvalid),
     .pcie_m_axi0_wdata  (pcie_dma_maxi[0].wdata),
     .pcie_m_axi0_wlast  (pcie_dma_maxi[0].wlast),
     .pcie_m_axi0_wready (pcie_dma_maxi[0].wready),
     .pcie_m_axi0_wstrb  (pcie_dma_maxi[0].wstrb),
     .pcie_m_axi0_wvalid (pcie_dma_maxi[0].wvalid),
 
-    // .pcie_m_axi1_araddr (pcie_dma_maxi[1].araddr),
-    // .pcie_m_axi1_arburst(pcie_dma_maxi[1].arburst),
-    // .pcie_m_axi1_arcache(pcie_dma_maxi[1].arcache),
-    // .pcie_m_axi1_arid   (0),
-    // .pcie_m_axi1_arlen  (pcie_dma_maxi[1].arlen),
-    // .pcie_m_axi1_arlock (pcie_dma_maxi[1].arlock),
-    // .pcie_m_axi1_arprot (pcie_dma_maxi[1].arprot),
-    // .pcie_m_axi1_arqos  (pcie_dma_maxi[1].arqos),
-    // .pcie_m_axi1_arready(pcie_dma_maxi[1].arready),
-    // .pcie_m_axi1_arsize (pcie_dma_maxi[1].arsize),
-    // .pcie_m_axi1_arvalid(pcie_dma_maxi[1].arvalid),
     .pcie_m_axi1_awaddr (pcie_dma_maxi[1].awaddr),
     .pcie_m_axi1_awburst(pcie_dma_maxi[1].awburst),
     .pcie_m_axi1_awcache(pcie_dma_maxi[1].awcache),
@@ -308,17 +320,51 @@ design_1 design_1_i
     .pcie_m_axi1_bready (pcie_dma_maxi[1].bready),
     .pcie_m_axi1_bresp  (pcie_dma_maxi[1].bresp),
     .pcie_m_axi1_bvalid (pcie_dma_maxi[1].bvalid),
-    // .pcie_m_axi1_rdata  (pcie_dma_maxi[1].rdata),
-    // .pcie_m_axi1_rid    (),
-    // .pcie_m_axi1_rlast  (pcie_dma_maxi[1].rlast),
-    // .pcie_m_axi1_rready (pcie_dma_maxi[1].rready),
-    // .pcie_m_axi1_rresp  (pcie_dma_maxi[1].rresp),
-    // .pcie_m_axi1_rvalid (pcie_dma_maxi[1].rvalid),
     .pcie_m_axi1_wdata  (pcie_dma_maxi[1].wdata),
     .pcie_m_axi1_wlast  (pcie_dma_maxi[1].wlast),
     .pcie_m_axi1_wready (pcie_dma_maxi[1].wready),
     .pcie_m_axi1_wstrb  (pcie_dma_maxi[1].wstrb),
-    .pcie_m_axi1_wvalid (pcie_dma_maxi[1].wvalid)    
+    .pcie_m_axi1_wvalid (pcie_dma_maxi[1].wvalid),
+
+    .pcie_m_axi2_awaddr (pcie_dma_maxi[2].awaddr),
+    .pcie_m_axi2_awburst(pcie_dma_maxi[2].awburst),
+    .pcie_m_axi2_awcache(pcie_dma_maxi[2].awcache),
+    .pcie_m_axi2_awlen  (pcie_dma_maxi[2].awlen),
+    .pcie_m_axi2_awlock (pcie_dma_maxi[2].awlock),
+    .pcie_m_axi2_awprot (pcie_dma_maxi[2].awprot),
+    .pcie_m_axi2_awqos  (pcie_dma_maxi[2].awqos),
+    .pcie_m_axi2_awready(pcie_dma_maxi[2].awready),
+    .pcie_m_axi2_awregion(4'b0000),
+    .pcie_m_axi2_awsize (pcie_dma_maxi[2].awsize),
+    .pcie_m_axi2_awvalid(pcie_dma_maxi[2].awvalid),
+    .pcie_m_axi2_bready (pcie_dma_maxi[2].bready),
+    .pcie_m_axi2_bresp  (pcie_dma_maxi[2].bresp),
+    .pcie_m_axi2_bvalid (pcie_dma_maxi[2].bvalid),
+    .pcie_m_axi2_wdata  (pcie_dma_maxi[2].wdata),
+    .pcie_m_axi2_wlast  (pcie_dma_maxi[2].wlast),
+    .pcie_m_axi2_wready (pcie_dma_maxi[2].wready),
+    .pcie_m_axi2_wstrb  (pcie_dma_maxi[2].wstrb),
+    .pcie_m_axi2_wvalid (pcie_dma_maxi[2].wvalid),
+    
+    .pcie_m_axi3_awaddr (pcie_dma_maxi[3].awaddr),
+    .pcie_m_axi3_awburst(pcie_dma_maxi[3].awburst),
+    .pcie_m_axi3_awcache(pcie_dma_maxi[3].awcache),
+    .pcie_m_axi3_awlen  (pcie_dma_maxi[3].awlen),
+    .pcie_m_axi3_awlock (pcie_dma_maxi[3].awlock),
+    .pcie_m_axi3_awprot (pcie_dma_maxi[3].awprot),
+    .pcie_m_axi3_awqos  (pcie_dma_maxi[3].awqos),
+    .pcie_m_axi3_awready(pcie_dma_maxi[3].awready),
+    .pcie_m_axi3_awregion(4'b0000),
+    .pcie_m_axi3_awsize (pcie_dma_maxi[3].awsize),
+    .pcie_m_axi3_awvalid(pcie_dma_maxi[3].awvalid),
+    .pcie_m_axi3_bready (pcie_dma_maxi[3].bready),
+    .pcie_m_axi3_bresp  (pcie_dma_maxi[3].bresp),
+    .pcie_m_axi3_bvalid (pcie_dma_maxi[3].bvalid),
+    .pcie_m_axi3_wdata  (pcie_dma_maxi[3].wdata),
+    .pcie_m_axi3_wlast  (pcie_dma_maxi[3].wlast),
+    .pcie_m_axi3_wready (pcie_dma_maxi[3].wready),
+    .pcie_m_axi3_wstrb  (pcie_dma_maxi[3].wstrb),
+    .pcie_m_axi3_wvalid (pcie_dma_maxi[3].wvalid)        
 
 );
 
@@ -330,12 +376,12 @@ util_reg util_reg_i
     
     .gpo(gpo),
     .gpi(gpi),
-    .fan_pwm(fan_pwm),
+    .fan_pwm(),
     .datecode(DATE_CODE),
     .timecode(TIME_CODE)         
 );  
 
-assign leds[0] = gpo[0];
+// assign leds[0] = gpo[0];
 
 
 
@@ -358,7 +404,7 @@ timing_engine timing_engine_i
 
 data_gen 
 # (
-    .NUM_CH(2)
+    .NUM_CH(NUM_DMA)
 ) data_gen_i (
     .ctrl_if(data_gen_if),
     .trigger(start_of_pulse),
@@ -372,9 +418,15 @@ axi_descriptor
 ) axi_descriptor_i 
 (
     .axi(descriptors_if),
+//    .descriptor_list('{{64'b0, 32'h00000000, 32'h10000}, 
+//                       {64'b0, 32'h01000000, 32'h20000},
+//                       {64'b0, 32'h01010000, 32'h20000}})
     .descriptor_list('{{64'b0, 32'h00000000, 32'h10000}, 
-                       {64'b0, 32'h01000000, 32'h20000},
-                       {64'b0, 32'h01010000, 32'h20000}})
+                       {64'b0, 32'h00100000, 32'h20000},
+                       {64'b0, 32'h00110000, 32'h20000},
+                       {64'b0, 32'h00120000, 32'h20000},
+                       {64'b0, 32'h00130000, 32'h20000}
+                    })
 );
     
 

project_1.srcs/sources_1/ip/axi_datamover_0_test/axi_datamover_0_test.xci

@@ -8,13 +8,13 @@
     "parameters": {
       "component_parameters": {
         "Component_Name": [ { "value": "axi_datamover_0_test", "resolve_type": "user", "usage": "all" } ],
-        "c_include_mm2s": [ { "value": "Omit", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "c_include_mm2s": [ { "value": "Omit", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "c_mm2s_stscmd_is_async": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_include_mm2s_dre": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
-        "c_include_mm2s_stsfifo": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "c_include_mm2s_stsfifo": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "c_mm2s_stscmd_fifo_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_mm2s_btt_used": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_mm2s_addr_pipe_depth": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -31,8 +31,8 @@
         "c_s2mm_addr_pipe_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "c_m_axi_s2mm_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "c_s2mm_support_indet_btt": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "c_mm2s_include_sf": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "c_s2mm_include_sf": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
+        "c_mm2s_include_sf": [ { "value": "false", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "c_s2mm_include_sf": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "c_m_axi_mm2s_id_width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_m_axi_mm2s_arid": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_m_axi_s2mm_id_width": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -74,7 +74,7 @@
         "C_S2MM_BTT_USED": [ { "value": "23", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S2MM_SUPPORT_INDET_BTT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S2MM_ADDR_PIPE_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_MM2S_INCLUDE_SF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S2MM_INCLUDE_SF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ENABLE_CACHE_USER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -86,11 +86,11 @@
         "C_CMD_WIDTH": [ { "value": "72", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -267,7 +267,7 @@
           "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
           "mode": "master",
           "parameters": {
-            "TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],

project_1.srcs/sources_1/ip/axi_datamover_256_0/axi_datamover_256_0.xci

@@ -8,13 +8,13 @@
     "parameters": {
       "component_parameters": {
         "Component_Name": [ { "value": "axi_datamover_256_0", "resolve_type": "user", "usage": "all" } ],
-        "c_include_mm2s": [ { "value": "Omit", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "c_include_mm2s": [ { "value": "Omit", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "c_mm2s_stscmd_is_async": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_include_mm2s_dre": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
-        "c_include_mm2s_stsfifo": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "c_include_mm2s_stsfifo": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "c_mm2s_stscmd_fifo_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_mm2s_btt_used": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_mm2s_addr_pipe_depth": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -31,8 +31,8 @@
         "c_s2mm_addr_pipe_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "c_m_axi_s2mm_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "c_s2mm_support_indet_btt": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "c_mm2s_include_sf": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "c_s2mm_include_sf": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "c_mm2s_include_sf": [ { "value": "false", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "c_s2mm_include_sf": [ { "value": "false", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "c_m_axi_mm2s_id_width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_m_axi_mm2s_arid": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "c_m_axi_s2mm_id_width": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -74,7 +74,7 @@
         "C_S2MM_BTT_USED": [ { "value": "23", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S2MM_SUPPORT_INDET_BTT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S2MM_ADDR_PIPE_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_MM2S_INCLUDE_SF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_S2MM_INCLUDE_SF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ENABLE_CACHE_USER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -86,11 +86,11 @@
         "C_CMD_WIDTH": [ { "value": "80", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
@@ -169,7 +169,7 @@
             "DATA_WIDTH": [ { "value": "256", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "AWUSER_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],

project_1.srcs/sources_1/ip/ch_data_buffer/ch_data_buffer.xci

@@ -34,7 +34,7 @@
         "Component_Name": [ { "value": "ch_data_buffer", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -52,11 +52,11 @@
         "C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.srcs/sources_1/ip/dma_ctrl_status_fifo_0/dma_ctrl_status_fifo_0.xci

@@ -16,8 +16,8 @@
         "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Input_Data_Width": [ { "value": "72", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "Input_Depth": [ { "value": "512", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "Output_Data_Width": [ { "value": "72", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Output_Depth": [ { "value": "512", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "72", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Depth": [ { "value": "512", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Use_Embedded_Registers": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -40,7 +40,7 @@
         "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "Use_Extra_Logic": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "Data_Count": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -51,11 +51,11 @@
         "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
-        "Full_Threshold_Assert_Value": [ { "value": "511", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
-        "Full_Threshold_Negate_Value": [ { "value": "510", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value": [ { "value": "511", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Negate_Value": [ { "value": "510", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
-        "Empty_Threshold_Assert_Value": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
-        "Empty_Threshold_Negate_Value": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
         "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -186,7 +186,7 @@
         "C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
         "C_DOUT_WIDTH": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ],
         "C_FULL_FLAGS_RST_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -381,11 +381,11 @@
         "C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynquplus" } ],
+        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xczu7ev" } ],
-        "PACKAGE": [ { "value": "ffvc1156" } ],
+        "DEVICE": [ { "value": "xcku15p" } ],
+        "PACKAGE": [ { "value": "ffve1517" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],

project_1.xpr

@@ -7,7 +7,7 @@
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="5035618c223548df9c6d60447429821e"/>
-    <Option Name="Part" Val="xczu7ev-ffvc1156-2-i"/>
+    <Option Name="Part" Val="xcku15p-ffve1517-2-i"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
     <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
@@ -64,13 +64,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="19"/>
-    <Option Name="WTModelSimExportSim" Val="19"/>
-    <Option Name="WTQuestaExportSim" Val="19"/>
+    <Option Name="WTXSimExportSim" Val="20"/>
+    <Option Name="WTModelSimExportSim" Val="20"/>
+    <Option Name="WTQuestaExportSim" Val="20"/>
     <Option Name="WTIesExportSim" Val="0"/>
-    <Option Name="WTVcsExportSim" Val="19"/>
-    <Option Name="WTRivieraExportSim" Val="19"/>
-    <Option Name="WTActivehdlExportSim" Val="19"/>
+    <Option Name="WTVcsExportSim" Val="20"/>
+    <Option Name="WTRivieraExportSim" Val="20"/>
+    <Option Name="WTActivehdlExportSim" Val="20"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -159,6 +159,14 @@
           <Attr Name="IsVisible" Val="1"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/ip/axi_datamover_0_test/axi_datamover_0_test.xci">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="top"/>
@@ -201,34 +209,6 @@
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
-    <FileSet Name="dma_ctrl_status_fifo_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dma_ctrl_status_fifo_0" RelGenDir="$PGENDIR/dma_ctrl_status_fifo_0">
-      <File Path="$PSRCDIR/sources_1/ip/dma_ctrl_status_fifo_0/dma_ctrl_status_fifo_0.xci">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <Config>
-        <Option Name="TopModule" Val="dma_ctrl_status_fifo_0"/>
-        <Option Name="dataflowViewerSettings" Val="min_width=16"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="axi_datamover_256_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_datamover_256_0" RelGenDir="$PGENDIR/axi_datamover_256_0">
-      <File Path="$PSRCDIR/sources_1/ip/axi_datamover_256_0/axi_datamover_256_0.xci">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <Config>
-        <Option Name="TopModule" Val="axi_datamover_256_0"/>
-        <Option Name="dataflowViewerSettings" Val="min_width=16"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
     <FileSet Name="design_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1" RelGenDir="$PGENDIR/design_1">
       <File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
         <FileInfo>
@@ -257,17 +237,30 @@
         <Option Name="UseBlackboxStub" Val="1"/>
       </Config>
     </FileSet>
-    <FileSet Name="axi_datamover_0_test" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_datamover_0_test" RelGenDir="$PGENDIR/axi_datamover_0_test">
-      <File Path="$PSRCDIR/sources_1/ip/axi_datamover_0_test/axi_datamover_0_test.xci">
+    <FileSet Name="dma_ctrl_status_fifo_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dma_ctrl_status_fifo_0" RelGenDir="$PGENDIR/dma_ctrl_status_fifo_0">
+      <File Path="$PSRCDIR/sources_1/ip/dma_ctrl_status_fifo_0/dma_ctrl_status_fifo_0.xci">
         <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
       <Config>
-        <Option Name="TopModule" Val="axi_datamover_0_test"/>
+        <Option Name="TopModule" Val="dma_ctrl_status_fifo_0"/>
+        <Option Name="dataflowViewerSettings" Val="min_width=16"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="axi_datamover_256_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_datamover_256_0" RelGenDir="$PGENDIR/axi_datamover_256_0">
+      <File Path="$PSRCDIR/sources_1/ip/axi_datamover_256_0/axi_datamover_256_0.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="axi_datamover_256_0"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
         <Option Name="UseBlackboxStub" Val="1"/>
       </Config>
@@ -295,7 +288,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku15p-ffve1517-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
@@ -305,7 +298,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="dma_ctrl_status_fifo_0_synth_1" Type="Ft3:Synth" SrcSet="dma_ctrl_status_fifo_0" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="dma_ctrl_status_fifo_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dma_ctrl_status_fifo_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_synth_1">
+    <Run Id="design_1_synth_1" Type="Ft3:Synth" SrcSet="design_1" Part="xcku15p-ffve1517-2-i" ConstrsSet="design_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
@@ -315,7 +308,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="axi_datamover_256_0_synth_1" Type="Ft3:Synth" SrcSet="axi_datamover_256_0" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="axi_datamover_256_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_datamover_256_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_synth_1">
+    <Run Id="ch_data_buffer_synth_1" Type="Ft3:Synth" SrcSet="ch_data_buffer" Part="xcku15p-ffve1517-2-i" ConstrsSet="ch_data_buffer" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ch_data_buffer_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ch_data_buffer_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ch_data_buffer_synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
@@ -325,7 +318,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="design_1_synth_1" Type="Ft3:Synth" SrcSet="design_1" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="design_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_synth_1">
+    <Run Id="dma_ctrl_status_fifo_0_synth_1" Type="Ft3:Synth" SrcSet="dma_ctrl_status_fifo_0" Part="xcku15p-ffve1517-2-i" ConstrsSet="dma_ctrl_status_fifo_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dma_ctrl_status_fifo_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
@@ -335,7 +328,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="ch_data_buffer_synth_1" Type="Ft3:Synth" SrcSet="ch_data_buffer" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="ch_data_buffer" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ch_data_buffer_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ch_data_buffer_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ch_data_buffer_synth_1">
+    <Run Id="axi_datamover_256_0_synth_1" Type="Ft3:Synth" SrcSet="axi_datamover_256_0" Part="xcku15p-ffve1517-2-i" ConstrsSet="axi_datamover_256_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_datamover_256_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
@@ -345,17 +338,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="axi_datamover_0_test_synth_1" Type="Ft3:Synth" SrcSet="axi_datamover_0_test" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="axi_datamover_0_test" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_datamover_0_test_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_0_test_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_0_test_synth_1">
-      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
-        <Step Id="synth_design"/>
-      </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
-      <RQSFiles/>
-    </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku15p-ffve1517-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
@@ -373,7 +356,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="dma_ctrl_status_fifo_0_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="dma_ctrl_status_fifo_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dma_ctrl_status_fifo_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_impl_1">
+    <Run Id="design_1_impl_1" Type="Ft2:EntireDesign" Part="xcku15p-ffve1517-2-i" ConstrsSet="design_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
@@ -390,7 +373,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="axi_datamover_256_0_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="axi_datamover_256_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_datamover_256_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_impl_1">
+    <Run Id="ch_data_buffer_impl_1" Type="Ft2:EntireDesign" Part="xcku15p-ffve1517-2-i" ConstrsSet="ch_data_buffer" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ch_data_buffer_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ch_data_buffer_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ch_data_buffer_impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
@@ -407,7 +390,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="design_1_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="design_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_impl_1">
+    <Run Id="dma_ctrl_status_fifo_0_impl_1" Type="Ft2:EntireDesign" Part="xcku15p-ffve1517-2-i" ConstrsSet="dma_ctrl_status_fifo_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dma_ctrl_status_fifo_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
@@ -424,24 +407,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="ch_data_buffer_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="ch_data_buffer" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ch_data_buffer_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ch_data_buffer_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ch_data_buffer_impl_1">
-      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
-        <Step Id="init_design"/>
-        <Step Id="opt_design"/>
-        <Step Id="power_opt_design"/>
-        <Step Id="place_design"/>
-        <Step Id="post_place_power_opt_design"/>
-        <Step Id="phys_opt_design"/>
-        <Step Id="route_design"/>
-        <Step Id="post_route_phys_opt_design"/>
-        <Step Id="write_bitstream"/>
-      </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
-      <RQSFiles/>
-    </Run>
-    <Run Id="axi_datamover_0_test_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="axi_datamover_0_test" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_datamover_0_test_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_0_test_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_0_test_impl_1">
+    <Run Id="axi_datamover_256_0_impl_1" Type="Ft2:EntireDesign" Part="xcku15p-ffve1517-2-i" ConstrsSet="axi_datamover_256_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_datamover_256_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>