bkiedinger@gmail.com ef68f51d09 fixing pulse gen bugs

2025-11-19 20:57:42 -06:00

..

verilog_ethernet

updated udp packet fragmentation so that we don't have to restrict number of samples to be a multiple of a fixed udp packet size

2025-07-15 22:40:15 -05:00

wfg_ofdm

added latency to freq mult to improve timing, had to delete and remake the IP core for some reason

2025-11-12 20:45:54 -06:00

axi_intf.sv

gitting project in git

2025-03-30 21:43:59 -05:00

axil_slave.v

gitting project in git

2025-03-30 21:43:59 -05:00

delay_shift_reg.sv

added latency to freq mult to improve timing, had to delete and remake the IP core for some reason

2025-11-12 20:45:54 -06:00

digital_rx_chain.sv

renamed system verilog files to have .sv extensions

2025-11-12 21:33:16 -06:00

ethernet_top.sv

renamed system verilog files to have .sv extensions

2025-11-12 21:33:16 -06:00

pulse_generator.v

fixing pulse gen bugs

2025-11-19 20:57:42 -06:00

spi.v

gitting project in git

2025-03-30 21:43:59 -05:00

timing_engine.sv

fixing pulse gen bugs

2025-11-19 20:57:42 -06:00

top.sv

renamed system verilog files to have .sv extensions

2025-11-12 21:33:16 -06:00

util_reg.sv

renamed system verilog files to have .sv extensions

2025-11-12 21:33:16 -06:00

waveform_gen.sv

renamed system verilog files to have .sv extensions

2025-11-12 21:33:16 -06:00