bkiedinger@gmail.com 316ae900ae version number and reverified data recording rate

2025-06-08 16:34:22 -05:00

..

verilog_ethernet

gitting project in git

2025-03-30 21:43:59 -05:00

axi_intf.sv

gitting project in git

2025-03-30 21:43:59 -05:00

axil_slave.v

gitting project in git

2025-03-30 21:43:59 -05:00

digital_rx_chain.v

updates

2025-05-20 20:33:12 -05:00

ethernet_top.v

gitting project in git

2025-03-30 21:43:59 -05:00

pulse_generator.v

this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

2025-04-25 06:26:07 -05:00

spi.v

gitting project in git

2025-03-30 21:43:59 -05:00

timing_engine.v

this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

2025-04-25 06:26:07 -05:00

top.v

version number and reverified data recording rate

2025-06-08 16:34:22 -05:00

util_reg.v

version number and reverified data recording rate

2025-06-08 16:34:22 -05:00

waveform_gen.v

last update to chris

2025-05-29 20:47:32 -05:00