bkiedinger@gmail.com 086c5dd9f3 starting wfg

2025-09-28 08:55:19 -05:00

..

verilog_ethernet

updated udp packet fragmentation so that we don't have to restrict number of samples to be a multiple of a fixed udp packet size

2025-07-15 22:40:15 -05:00

wfg_ofdm

starting wfg

2025-09-28 08:55:19 -05:00

axi_intf.sv

gitting project in git

2025-03-30 21:43:59 -05:00

axil_slave.v

gitting project in git

2025-03-30 21:43:59 -05:00

digital_rx_chain.v

decimation working

2025-06-11 08:36:31 -05:00

ethernet_top.v

updated udp packet fragmentation so that we don't have to restrict number of samples to be a multiple of a fixed udp packet size

2025-07-15 22:40:15 -05:00

pulse_generator.v

this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

2025-04-25 06:26:07 -05:00

spi.v

gitting project in git

2025-03-30 21:43:59 -05:00

timing_engine.v

this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ

2025-04-25 06:26:07 -05:00

top.v

updated udp packet fragmentation so that we don't have to restrict number of samples to be a multiple of a fixed udp packet size

2025-07-15 22:40:15 -05:00

util_reg.v

updated udp packet fragmentation so that we don't have to restrict number of samples to be a multiple of a fixed udp packet size

2025-07-15 22:40:15 -05:00

waveform_gen.v

support for multiple waveforms

2025-06-29 20:18:52 -05:00