fixing pulse gen bugs

renamed system verilog files to have .sv extensions
added latency to freq mult to improve timing, had to delete and remake the IP core for some reason
2025-11-19 20:57:42 -06:00 · 2025-11-12 21:33:16 -06:00 · 2025-11-12 20:45:54 -06:00 · 2025-11-12 09:09:57 -06:00 · 2025-11-12 08:52:44 -06:00 · 2025-10-18 12:28:43 -05:00
27 changed files with 1203 additions and 142 deletions
--- a/python/waveform_generator/hdl_sim_check_results.py
+++ b/python/waveform_generator/hdl_sim_check_results.py
@@ -2,6 +2,8 @@ from matplotlib import pyplot as plt
 from ctypes import *
 import numpy as np

+from read_data_file import db20n
+

 def read_sim_output(filename, is_float=False):
    fid = open(filename, "r")
@@ -24,10 +26,27 @@ def main():
    data[data >= 2**15] -= 2**16
    data = data[0::2] + 1j * data[1::2]

+
+    x = np.fft.fft(data)
+    f_axis = np.fft.fftfreq(x.size, d=1/750)
+
+    x = np.fft.fftshift(x)
+    f_axis = np.fft.fftshift(f_axis)
+
+
+    plt.figure()
+    plt.plot(f_axis, db20n(x))
+
+
    plt.figure()
    plt.plot(data.real)
    plt.plot(data.imag)
-    plt.title('Sim Output')
+    plt.title('HDL Sim Output - IQ')
+    plt.grid()
+
+    plt.figure()
+    plt.plot(np.unwrap(np.angle(data)))
+    plt.title('HDL Sim Output - Phase')
    plt.grid()

    plt.show()
--- a/python/waveform_generator/hdl_sim_config.py
+++ b/python/waveform_generator/hdl_sim_config.py
@@ -5,10 +5,16 @@ def main():
    f = 10e6
    n = 4096

+    start_freq = -20507812.5
+    start_freq = start_freq/fs * 2**32
+    if (start_freq < 0):
+        start_freq += 2**32
+    print(start_freq)

-    freq = f/fs * 2**31
+    delta_freq = 5859375
+    delta_freq = delta_freq/fs * 2**32
+    print(delta_freq)

-    print(freq)

 if __name__ == '__main__':
    main()
--- a/python/waveform_generator/wf_ofdm.py
+++ b/python/waveform_generator/wf_ofdm.py
@@ -118,8 +118,8 @@ def wg_ofdm():
    do_agile = False
    n_sub_cpi = 1
    n_tx = 1
-    n_rx = 2
-    n_pol = 2
+    n_rx = 1
+    n_pol = 1

    n_samp = 64
    n_samp_chip = 8
@@ -237,6 +237,7 @@ def wg_ofdm():
        get_pulse_params(n_tx, n_rx, f_samp, n_samp_chip, n_f, n_f_pulse, n_sub_cpi, n_pol, p))

    print(baseband/1e6)
+    print(start_phase)

    pulse, _phase = get_waveform(baseband,
                                 start_phase,
@@ -247,15 +248,27 @@ def wg_ofdm():
                                 n_samp * tx_sample_rate_multiplier,
                                 f_samp * tx_sample_rate_multiplier)

+    print('Num Chips', baseband.size)
+    print('Start Freq', baseband[0])
+    print('Delta Freq', np.unique(np.diff(baseband)))
+
    pulse = np.squeeze(pulse)

    plt.figure()
-    plt.plot(pulse[0, :].real)
-    plt.plot(pulse[0, :].imag)
+    plt.plot(pulse.real)
+    plt.plot(pulse.imag)
+    plt.title('Python Output - IQ')
+    plt.grid()

    plt.figure()
-    plt.plot(pulse[1, :].real)
-    plt.plot(pulse[1, :].imag)
+    plt.plot(np.unwrap(np.angle(pulse)))
+    # plt.plot(np.angle(pulse), '.-')
+    plt.title('Python Output - Phase')
+    plt.grid()
+
+    # plt.figure()
+    # plt.plot(pulse[1, :].real)
+    # plt.plot(pulse[1, :].imag)

    plt.show()

--- a/python/waveform_generator/wf_ofdm_simple.py
+++ b/python/waveform_generator/wf_ofdm_simple.py
@@ -0,0 +1,47 @@
+import numpy as np
+from matplotlib import pyplot as plt
+
+
+def wg_ofdm():
+
+    tx_sample_rate = 750e6
+    rx_decimation = 16
+    rx_sample_rate = tx_sample_rate / rx_decimation
+    n_rx_samp_per_chip = 16   # Keep at >= x2 of num_chips and start phase will always be 0, if num chips is power of 2?
+    num_chips = 8
+    n_tx_samp_per_chip = n_rx_samp_per_chip * rx_decimation
+    n_tx_samp_per_pulse = n_tx_samp_per_chip * num_chips
+
+    print(n_tx_samp_per_chip / 4)
+
+    chip_freq = (np.arange(num_chips) - num_chips//2 + 0.5)/num_chips * rx_sample_rate
+
+    # First, generate simple in order waveform
+    freq = np.repeat(chip_freq, n_tx_samp_per_chip)
+
+    phase = freq / tx_sample_rate
+    phase = np.cumsum(np.concatenate([[0], phase]))
+    phase = phase[0:-1]
+
+    # Extract the start phases of each chip, ideally these are always 0
+    chip_start_phase = phase[0::n_tx_samp_per_chip] % 1
+    print(chip_start_phase)
+    print(chip_start_phase * 2**16)
+    print(chip_freq)
+
+    x = np.exp(1j * 2 * np.pi * phase)
+
+    plt.figure()
+    plt.plot(x.real)
+    plt.plot(x.imag)
+
+    plt.figure()
+    plt.plot(np.unwrap(np.angle(x)))
+
+    plt.show()
+
+
+    return
+
+if __name__ == '__main__':
+    wg_ofdm()
--- a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/decimation_bd.bda
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/decimation_bd.bda
@@ -23,20 +23,20 @@
  <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
  <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
    <node id="n0">
+      <data key="VM">decimation_bd</data>
+      <data key="VT">BC</data>
+    </node>
+    <node id="n1">
      <data key="VH">2</data>
      <data key="VM">decimation_bd</data>
      <data key="VT">VR</data>
    </node>
-    <node id="n1">
+    <node id="n2">
      <data key="TU">active</data>
      <data key="VH">2</data>
      <data key="VT">PM</data>
    </node>
-    <node id="n2">
-      <data key="VM">decimation_bd</data>
-      <data key="VT">BC</data>
-    </node>
-    <edge id="e0" source="n2" target="n0"/>
-    <edge id="e1" source="n0" target="n1"/>
+    <edge id="e0" source="n0" target="n1"/>
+    <edge id="e1" source="n1" target="n2"/>
  </graph>
 </graphml>
--- a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_0/decimation_bd_axis_broadcaster_0_0.xci
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_0/decimation_bd_axis_broadcaster_0_0.xci
@@ -187,7 +187,7 @@ imum {}} value data_valid} enabled {attribs {resolve_type generated dependency d
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
-            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+            "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "aresetn" } ]
@@ -206,7 +206,7 @@ imum {}} value data_valid} enabled {attribs {resolve_type generated dependency d
            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_CLKEN": [ { "value": "aclken", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "CLK": [ { "physical_name": "aclk" } ]
--- a/radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv
@@ -0,0 +1,47 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module delay_shift_register #(
+  parameter DELAY_CYCLES = 4 ,
+  parameter DATA_WIDTH = 1
+) (
+  input  wire clk,
+  input  wire reset, 
+  input  wire [DATA_WIDTH-1:0] data_in,
+  output wire [DATA_WIDTH-1:0] data_out
+);
+
+  // // Declare a register to hold the shifted data
+  // reg [DELAY_CYCLES-1:0] shift_reg;
+
+  // always @ (posedge clk) begin
+  //   if (reset) begin
+  //     shift_reg <= '0;
+  //   end else begin
+  //     shift_reg <= {shift_reg[DELAY_CYCLES-2:0], data_in};
+  //   end
+  // end
+
+  // assign data_out = shift_reg[DELAY_CYCLES-1];
+
+  // Declare a register to hold the shifted data
+  reg [DATA_WIDTH-1:0] shift_reg [DELAY_CYCLES];
+
+  always @ (posedge clk) begin
+    if (reset) begin
+        for (int i = 0; i < DELAY_CYCLES; i = i + 1) begin
+            shift_reg[i] <= 0;
+        end
+    end else begin
+        for (int i = DELAY_CYCLES-1; i > 0; i = i - 1) begin
+            shift_reg[i] <= shift_reg[i-1]; // Shift right
+        end
+        shift_reg[0] <= data_in;
+    end
+  end
+
+  assign data_out = shift_reg[DELAY_CYCLES-1];
+
+endmodule
+`resetall
--- a/radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.sv
--- a/radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.sv
--- a/radar_alinx_kintex.srcs/sources_1/hdl/pulse_generator.v
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/pulse_generator.v
@@ -10,7 +10,7 @@ module pulse_generator #
    input  wire                     clk,
    input  wire                     rst,
    input  wire [COUNTER_BITS-1:0]  pulse_length,
-    output wire                     start_of_pulse,
+    input  wire                     start_of_pulse,
    output wire                     pulse_out
 );

@@ -22,9 +22,11 @@ assign pulse_out = pulse_active;
 always @ (posedge clk) begin
    if (rst == 1'b1) begin
        pulse_cnt <= 0;
+        pulse_active <= 0;
    end else begin
        if (start_of_pulse) begin
            pulse_active <= 1;
+            pulse_cnt <= pulse_length;
        end

        if (pulse_active) begin
@@ -38,7 +40,6 @@ always @ (posedge clk) begin
 end


-
 endmodule


--- a/radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.sv
@@ -403,7 +403,7 @@ genvar j;
 generate
    for (j = 0; j < NUM_TIMING_PULSES; j = j + 1) begin
    
-        assign timing_pulses[j] =  timing_pulses_i | reg_pulse_start[j][28];
+        assign timing_pulses[j] =  timing_pulses_i[j] | reg_pulse_start[j][28];
    
        always @ (posedge clk) begin
            if (pri_cnt == reg_pulse_start[j][27:0]) begin
@@ -413,7 +413,7 @@ generate
            end
        end
    
-        pulse_generator (
+        pulse_generator pulse_generator_i(
            .clk(clk),
            .rst(rst),
            .pulse_length(reg_pulse_width[j]),
--- a/radar_alinx_kintex.srcs/sources_1/hdl/top.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/top.sv
@@ -945,47 +945,67 @@ module top #
    assign jesd_axis_tx_cmd_tdata = 0;
    assign jesd_axis_tx_cmd_tvalid = 1'b1;

-    waveform_gen waveform_gen_i (
-        .clk(jesd_core_clk),
-        
+    wire [127:0] iq_out;
+    wire iq_out_valid;
+
+    gen_ofdm waveform_gen_i (
+        .clk(jesd_core_clk),    
+        .reset(1'b0),
+
        .ctrl_if(wf_gen_if),
+        .start_pulse(start_of_pulse),
+        .iq_out(iq_out),
+        .iq_out_valid(iq_out_valid)
+    );
+    
+    assign dac0_wf_bram_dout = 0;
+    assign dac1_wf_bram_dout = 0;
+    assign dac2_wf_bram_dout = 0;
+    assign dac3_wf_bram_dout = 0;

-        .start_of_pulse(start_of_pulse),
-        
-        .dac0_wf_bram_addr(dac0_wf_bram_addr),
-        .dac0_wf_bram_clk(dac0_wf_bram_clk),
-        .dac0_wf_bram_din(dac0_wf_bram_din),
-        .dac0_wf_bram_dout(dac0_wf_bram_dout),
-        .dac0_wf_bram_en(dac0_wf_bram_en),
-        .dac0_wf_bram_rst(dac0_wf_bram_rst),
-        .dac0_wf_bram_we(dac0_wf_bram_we),
-        
-        .dac1_wf_bram_addr(dac1_wf_bram_addr),
-        .dac1_wf_bram_clk(dac1_wf_bram_clk),
-        .dac1_wf_bram_din(dac1_wf_bram_din),
-        .dac1_wf_bram_dout(dac1_wf_bram_dout),
-        .dac1_wf_bram_en(dac1_wf_bram_en),
-        .dac1_wf_bram_rst(dac1_wf_bram_rst),
-        .dac1_wf_bram_we(dac1_wf_bram_we),
-        
-        .dac2_wf_bram_addr(dac2_wf_bram_addr),
-        .dac2_wf_bram_clk(dac2_wf_bram_clk),
-        .dac2_wf_bram_din(dac2_wf_bram_din),
-        .dac2_wf_bram_dout(dac2_wf_bram_dout),
-        .dac2_wf_bram_en(dac2_wf_bram_en),
-        .dac2_wf_bram_rst(dac2_wf_bram_rst),
-        .dac2_wf_bram_we(dac2_wf_bram_we),
-        
-        .dac3_wf_bram_addr(dac3_wf_bram_addr),
-        .dac3_wf_bram_clk(dac3_wf_bram_clk),
-        .dac3_wf_bram_din(dac3_wf_bram_din),
-        .dac3_wf_bram_dout(dac3_wf_bram_dout),
-        .dac3_wf_bram_en(dac3_wf_bram_en),
-        .dac3_wf_bram_rst(dac3_wf_bram_rst),
-        .dac3_wf_bram_we(dac3_wf_bram_we),
+    assign jesd_axis_tx_tdata = {iq_out, iq_out, iq_out, iq_out};

-        .jesd_tx(jesd_axis_tx_tdata)
-    );        
+    // waveform_gen waveform_gen_i (
+    //     .clk(jesd_core_clk),
+        
+    //     .ctrl_if(wf_gen_if),
+
+    //     .start_of_pulse(start_of_pulse),
+        
+    //     .dac0_wf_bram_addr(dac0_wf_bram_addr),
+    //     .dac0_wf_bram_clk(dac0_wf_bram_clk),
+    //     .dac0_wf_bram_din(dac0_wf_bram_din),
+    //     .dac0_wf_bram_dout(dac0_wf_bram_dout),
+    //     .dac0_wf_bram_en(dac0_wf_bram_en),
+    //     .dac0_wf_bram_rst(dac0_wf_bram_rst),
+    //     .dac0_wf_bram_we(dac0_wf_bram_we),
+        
+    //     .dac1_wf_bram_addr(dac1_wf_bram_addr),
+    //     .dac1_wf_bram_clk(dac1_wf_bram_clk),
+    //     .dac1_wf_bram_din(dac1_wf_bram_din),
+    //     .dac1_wf_bram_dout(dac1_wf_bram_dout),
+    //     .dac1_wf_bram_en(dac1_wf_bram_en),
+    //     .dac1_wf_bram_rst(dac1_wf_bram_rst),
+    //     .dac1_wf_bram_we(dac1_wf_bram_we),
+        
+    //     .dac2_wf_bram_addr(dac2_wf_bram_addr),
+    //     .dac2_wf_bram_clk(dac2_wf_bram_clk),
+    //     .dac2_wf_bram_din(dac2_wf_bram_din),
+    //     .dac2_wf_bram_dout(dac2_wf_bram_dout),
+    //     .dac2_wf_bram_en(dac2_wf_bram_en),
+    //     .dac2_wf_bram_rst(dac2_wf_bram_rst),
+    //     .dac2_wf_bram_we(dac2_wf_bram_we),
+        
+    //     .dac3_wf_bram_addr(dac3_wf_bram_addr),
+    //     .dac3_wf_bram_clk(dac3_wf_bram_clk),
+    //     .dac3_wf_bram_din(dac3_wf_bram_din),
+    //     .dac3_wf_bram_dout(dac3_wf_bram_dout),
+    //     .dac3_wf_bram_en(dac3_wf_bram_en),
+    //     .dac3_wf_bram_rst(dac3_wf_bram_rst),
+    //     .dac3_wf_bram_we(dac3_wf_bram_we),
+
+    //     .jesd_tx(jesd_axis_tx_tdata)
+    // );        


 endmodule
--- a/radar_alinx_kintex.srcs/sources_1/hdl/util_reg.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/util_reg.sv
--- a/radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.sv
--- a/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv
@@ -2,6 +2,75 @@
 `timescale 1ns / 1ps
 `default_nettype none

+// Outputs 4 IQ samples in parallel for connection to DAC interface
+
+// start_pulse - Kicks off output for a single pulse, expected to be a single clock wide
+// start_table_irq - This is used to indicate to software that playback from the top of the sequence table has begin
+// half_table_irq - This is used to indicate to software that playback from the mid point of the sequence table has begin
+//                  The mid point is defined as (n_total_chips >> 1)
+// These interrupts are used in combination to enable software to continually update the sequence table in a ping pong 
+// fashion while the system is operating
+
+/*
+* ADDR=0x0000 Control Register (reg_ctrl)  
+* Currently unused
+*/
+
+/*
+* ADDR=0x0004 Start Frequency Register (reg_start_freq)  
+* Sets the value of the lowest frequency chip, final chip frequincies are calculated using this value, 
+* the delta frequency, and the sequence number from the ram
+* Bit 31:0: Frequency
+*/
+
+/*
+* ADDR=0x0008 Chip Description 0 (reg_chips_0)  
+* Bit 15:0: Number of total chips in the sequence table
+*/
+
+/*
+* ADDR=0x000C Chip Description 1 (reg_chips_1)  
+* Bit 15:0: Number of DAC samples per chip divided by 4 (due to parallel output of 4 samples)
+* Bit 31:16: Number of Chips per Pulse
+*/
+
+/*
+* ADDR=0x0010 Delta Frequency Register (reg_start_freq)  
+* Sets the delta frequency value between chips, final chip frequincies are calculated using this value, 
+* the delta frequency, and the sequence number from the ram
+* Bit 31:0: Delta Frequency
+*/
+
+/*
+* ADDR=0x0014 Currently Unused
+*/
+
+/*
+* ADDR=0x0018 Sequence Memory Write Address
+* Sets the write address of the sequence memory
+* Bit 15:0: BRAM Write Address 
+*/
+
+/*
+* ADDR=0x001C Sequence Memory Write Data
+* Write a value into the sequence BRAM, and automatically increments the address.  
+* Repeated writes to this registers store values in sequential address in the BRAM
+* Bit 15:0: BRAM Write Data 
+*/
+
+/*
+* ADDR=0x0020 Start Phase Memory Write Address
+* Sets the write address of the sequence memory
+* Bit 15:0: BRAM Write Address 
+*/
+
+/*
+* ADDR=0x0024 Start Phase Memory Write Data
+* Write a value into the sequence BRAM, and automatically increments the address.  
+* Repeated writes to this registers store values in sequential address in the BRAM
+* Bit 15:0: BRAM Write Data 
+*/
+
 module gen_ofdm # (
    parameter integer AXI_ADDR_WIDTH	= 32,
    parameter integer AXI_DATA_WIDTH	= 32	
@@ -13,10 +82,50 @@ module gen_ofdm # (

 	input  wire 	   start_pulse,

+    output wire         start_table_irq,
+    output wire         half_table_irq,
    output wire [127:0] iq_out,
 	output wire         iq_out_valid
 );

+// ------------------------------
+// BRAM for holding sequence
+// ------------------------------
+wire [15:0] read_addr;
+wire [15:0] read_sequence;
+reg bram_we;
+reg [15:0] bram_waddr;
+reg [15:0] bram_wdata;
+
+ofdm_sequence_ram sequence_ram (
+  .clka(ctrl_if.clk), 
+  .ena(1'b1),
+  .wea(bram_we),    
+  .addra(bram_waddr),
+  .dina(bram_wdata), 
+  .clkb(clk),
+  .enb(1'b1),
+  .addrb(read_addr),
+  .doutb(read_sequence) 
+);
+
+wire [15:0] read_phase;
+reg phase_bram_we;
+reg [15:0] phase_bram_waddr;
+reg [15:0] phase_bram_wdata;
+
+ofdm_sequence_ram phase_ram (
+  .clka(ctrl_if.clk), 
+  .ena(1'b1),
+  .wea(phase_bram_we),    
+  .addra(phase_bram_waddr),
+  .dina(phase_bram_wdata), 
+  .clkb(clk),
+  .enb(1'b1),
+  .addrb(read_addr),
+  .doutb(read_phase) 
+);
+
 // ------------------------------
 // AXIL Decode
 // ------------------------------
@@ -69,39 +178,79 @@ axil_slave
 // Config Registers
 // ------------------------------
 reg [31:0]  reg_ctrl;
-reg [31:0]  reg_freq;
-reg [31:0]  reg_phase;
-reg [31:0]  reg_chips;
+reg [31:0]  reg_start_freq;
+reg [31:0]  reg_delta_freq;
+reg [31:0]  reg_delta_phase;
+reg [31:0]  reg_chips_0;
+reg [31:0]  reg_chips_1;

 always @ (posedge ctrl_if.clk) begin
    if (~ctrl_if.resetn) begin
        reg_ctrl <= 0;
-        reg_freq <= 0;
-        reg_phase <= 0;
+        reg_start_freq <= 0;
+		reg_delta_freq <= 0;
+        reg_chips_0 <= 0;
+        reg_chips_1 <= 0;
+		reg_delta_phase <= 0;
+		bram_we <= 1'b0;
+		bram_waddr <= 0;
+		bram_wdata <= 0;
+		phase_bram_we <= 1'b0;
+		phase_bram_waddr <= 0;
+		phase_bram_wdata <= 0;		
    end else begin
+
+		bram_we <= 1'b0;
+		if (bram_we) begin
+			bram_waddr <= bram_waddr + 1;
+		end
+
+		phase_bram_we <= 1'b0;
+		if (phase_bram_we) begin
+			phase_bram_waddr <= phase_bram_waddr + 1;
+		end		
+
        if (wren) begin
            if (waddr[11:0] == 'h000) begin
                reg_ctrl <= wdata;
            end
            if (waddr[11:0] == 'h004) begin
-                reg_freq <= wdata;
+                reg_start_freq <= wdata;
            end
            if (waddr[11:0] == 'h008) begin
-                reg_phase <= wdata;
+                reg_chips_0 <= wdata;
            end 
            if (waddr[11:0] == 'h00C) begin
-                reg_chips <= wdata;
+                reg_chips_1 <= wdata;
            end      
-            // if (waddr[11:0] == 'h010) begin
-            //     reg_phase <= wdata;
-            // end      						                       
+            if (waddr[11:0] == 'h010) begin
+                reg_delta_freq <= wdata;
+            end    
+            if (waddr[11:0] == 'h014) begin
+                reg_delta_phase <= wdata;
+            end				
+			if (waddr[11:0] == 'h018) begin
+                bram_waddr <= wdata;
+            end				  
+            if (waddr[11:0] == 'h01C) begin
+				bram_we <= 1'b1;
+                bram_wdata <= wdata;
+            end				
+			if (waddr[11:0] == 'h020) begin
+                phase_bram_waddr <= wdata;
+            end				  
+            if (waddr[11:0] == 'h024) begin
+				phase_bram_we <= 1'b1;
+                phase_bram_wdata <= wdata;
+            end													                       
        end
    end
 end

-wire [15:0] n_samp_chip = reg_chips[15:0];
-wire [15:0] n_chip = reg_chips[31:16];
+wire [15:0] n_total_chips = reg_chips_0[15:0];

+wire [15:0] n_samp_per_chip = reg_chips_1[15:0];
+wire [15:0] n_chip_per_pulse = reg_chips_1[31:16];

 // ------------------------------
 // Bla
@@ -109,47 +258,128 @@ wire [15:0] n_chip = reg_chips[31:16];
 reg [24:0] pulse_cnt;
 reg [15:0] chip_cnt;
 reg [15:0] chip_ind;
+reg [15:0] chip_per_pulse_cnt;
 reg pulse_active;
-reg start_of_pulse;
+wire set_phase;
+reg start_irq;
+reg half_irq;
+
+assign read_addr = chip_ind;
+assign start_table_irq = start_irq;
+assign half_table_irq = half_irq;

 always @ (posedge clk) begin
 	if (reset) begin
 		chip_cnt <= 0;
 		chip_ind <= 0;
+        chip_per_pulse_cnt <= 0;
 		pulse_active <= 1'b0;
-		start_of_pulse <= 1'b0;
 	end else begin
-		start_of_pulse <= 1'b0;
 		if (start_pulse) begin
 			chip_cnt <= 0;
-			chip_ind <= 0;
+            chip_per_pulse_cnt <= 0;
 			pulse_active <= 1'b1;
-			start_of_pulse <= 1'b1;
 		end

 		if (pulse_active) begin
 			chip_cnt <= chip_cnt + 1;
-			if (chip_cnt == n_samp_chip - 1) begin
+			if (chip_cnt == n_samp_per_chip - 1) begin
 				chip_cnt <= 0;
 				chip_ind <= chip_ind + 1;
-				if (chip_ind == n_chip - 1) begin
-					chip_ind <= 0;
-					pulse_active = 1'b0;
+                chip_per_pulse_cnt <= chip_per_pulse_cnt + 1;
+				if (chip_per_pulse_cnt == n_chip_per_pulse - 1) begin
+					chip_per_pulse_cnt <= 0;
+					pulse_active <= 1'b0;
+                    if (chip_ind == n_total_chips-1) begin
+                        chip_ind <= 0;
+                    end
 				end
 			end
 		end
+
+        start_irq <= 1'b0;
+        if (pulse_active) begin
+            if (chip_cnt == 0) begin
+                if (chip_ind == 0) begin
+                    start_irq <= 1'b1;
+                end
+            end
+        end
+
+        half_irq <= 1'b0;
+        if (pulse_active) begin
+            if (chip_cnt == 0) begin
+                if (chip_ind == (n_total_chips >> 1)) begin
+                    half_irq <= 1'b1;
+                end
+            end
+        end        
+
+
 	end
 end

+wire [47:0] mult_out;
+wire [31:0] chip_delta_freq;
+freq_mult freq_mult (
+  .CLK(clk), 
+  .A(reg_delta_freq),  
+  .B(read_sequence),
+  .P(mult_out)
+);
+assign chip_delta_freq = mult_out[31:0];
+
+reg [31:0] chip_freq;
+reg [15:0] read_phase_q;
+reg [15:0] read_phase_q2;
+always @ (posedge clk) begin
+	chip_freq <= chip_delta_freq + reg_start_freq;
+    read_phase_q <= read_phase;
+    read_phase_q2 <= read_phase_q;
+end
+
+assign set_phase = (chip_cnt == 0) ? pulse_active : 1'b0;
+
+wire [15:0] read_phase_delayed;
+delay_shift_register # (
+    .DELAY_CYCLES(6),
+    .DATA_WIDTH(16)
+) delay_phase (
+  .clk(clk), 
+  .reset(reset),
+  .data_in(read_phase),    
+  .data_out(read_phase_delayed)
+);
+
+wire pulse_active_delayed;
+delay_shift_register # (
+    .DELAY_CYCLES(8)
+) delay_valid (
+  .clk(clk), 
+  .reset(reset),
+  .data_in(pulse_active),    
+  .data_out(pulse_active_delayed)
+);
+
+wire set_phase_delayed;
+delay_shift_register # (
+    .DELAY_CYCLES(8)
+) delay_set_phase (
+  .clk(clk), 
+  .reset(reset),
+  .data_in(set_phase),    
+  .data_out(set_phase_delayed)
+);


 gen_sine gen_sine_i (
    .clk(clk),
    .reset(reset),  
-    .set_phase(start_of_pulse),  
-	.valid(pulse_active),
-    .phase(reg_phase),
-    .frequency(reg_freq),
+    .set_phase(set_phase_delayed),  
+	.valid(pulse_active_delayed),
+    // .phase({read_phase_q2, 16'h0000}),
+    .phase({read_phase_delayed, 16'h0000}),
+    .frequency(chip_freq),
    .iq_out(iq_out),
 	.iq_out_valid(iq_out_valid)
 );
--- a/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv
@@ -24,6 +24,7 @@ reg        valid_q2;
 reg [31:0] phase_q;
 reg [31:0] frequency_q;
 reg [127:0] iq_out_i;
+wire [3:0] iq_out_valid_i;

 always @ (posedge clk) begin
    set_phase_q <= set_phase;
@@ -58,7 +59,7 @@ generate
            .aclk(clk),
            .s_axis_phase_tvalid(valid_q2),  
            .s_axis_phase_tdata(cordic_phase_in),  
-            .m_axis_dout_tvalid(iq_out_valid),
+            .m_axis_dout_tvalid(iq_out_valid_i[i]),
            .m_axis_dout_tdata(iq_out_i[i*32+31:i*32])  
        );
                
@@ -66,6 +67,7 @@ generate
 endgenerate  

 assign iq_out = iq_out_i;
+assign iq_out_valid = &iq_out_valid_i;

 endmodule
 `resetall
--- a/radar_alinx_kintex.srcs/sources_1/ip/freq_mult/freq_mult.xci
+++ b/radar_alinx_kintex.srcs/sources_1/ip/freq_mult/freq_mult.xci
@@ -0,0 +1,160 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "freq_mult",
+    "component_reference": "xilinx.com:ip:mult_gen:12.0",
+    "ip_revision": "18",
+    "gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/freq_mult",
+    "parameters": {
+      "component_parameters": {
+        "InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "freq_mult", "resolve_type": "user", "usage": "all" } ],
+        "MultType": [ { "value": "Parallel_Multiplier", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PortAType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
+        "PortAWidth": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PortBType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
+        "PortBWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ConstValue": [ { "value": "129", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "CcmImp": [ { "value": "Distributed_Memory", "resolve_type": "user", "usage": "all" } ],
+        "Multiplier_Construction": [ { "value": "Use_LUTs", "resolve_type": "user", "usage": "all" } ],
+        "OptGoal": [ { "value": "Speed", "resolve_type": "user", "usage": "all" } ],
+        "Use_Custom_Output_Width": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OutputWidthHigh": [ { "value": "47", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "OutputWidthLow": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "UseRounding": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RoundPoint": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PipeStages": [ { "value": "5", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "ClockEnable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SyncClear": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SclrCePriority": [ { "value": "SCLR_Overrides_CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "ZeroDetect": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MODEL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_GOAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_A_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_B_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_B_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUT_HIGH": [ { "value": "47", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUT_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CCM_IMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_B_VALUE": [ { "value": "10000001", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ZERO_DETECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ROUND_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ROUND_PT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintexu" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku040" } ],
+        "PACKAGE": [ { "value": "ffva1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "18" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/freq_mult" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "CLK": [ { "direction": "in", "driver_value": "0x1" } ],
+        "A": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "B": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "P": [ { "direction": "out", "size_left": "47", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "a_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "DATA": [ { "physical_name": "A" } ]
+          }
+        },
+        "clk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "p_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "CLK" } ]
+          }
+        },
+        "sclr_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "ce_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "b_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "DATA": [ { "physical_name": "B" } ]
+          }
+        },
+        "p_intf": {
+          "vlnv": "xilinx.com:signal:data:1.0",
+          "abstraction_type": "xilinx.com:signal:data_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "DATA": [ { "physical_name": "P" } ]
+          }
+        }
+      }
+    }
+  }
+}
--- a/radar_alinx_kintex.srcs/sources_1/ip/ofdm_sequence_ram/ofdm_sequence_ram.xci
+++ b/radar_alinx_kintex.srcs/sources_1/ip/ofdm_sequence_ram/ofdm_sequence_ram.xci
@@ -0,0 +1,281 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "ofdm_sequence_ram",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "5",
+    "gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/ofdm_sequence_ram",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "ofdm_sequence_ram", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
+        "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "Simple_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addrb" } ],
+            "CLK": [ { "physical_name": "clkb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ],
+            "EN": [ { "physical_name": "enb" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_1": {
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
--- a/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv
+++ b/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv
@@ -73,6 +73,11 @@ gen_ofdm dut (

 int fid_out;

+reg [15:0] n_samp_per_chip;
+reg [15:0] n_chip_per_pulse;
+reg [15:0] n_total_chips;
+reg [15:0] n_pulses;
+
 initial begin
    reset = 1'b1;
    clk = 1'b0;
@@ -87,21 +92,52 @@ initial begin
    reset = 1'b0;
    repeat(25) @(posedge clk);

+    n_samp_per_chip = 64;
+    n_chip_per_pulse = 8;
+    n_total_chips = 16;
+    n_pulses = 4;
+    
+
    // Set Control Regs
-    vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 0, resp);
-    vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 28633115, resp);
-    vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, 0, resp);
-    vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, ('h00010400), resp);
+        vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 4177526784, resp);      // Start Freq
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, n_total_chips, resp);             
+    vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, (n_chip_per_pulse << 16) | n_samp_per_chip, resp);
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0010, 0, 33554432, resp);        // Delta Freq
+
+    // Load Sequence
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0018, 0, 0, resp);  // Set Start Address
+    for (int i = 0; i < 8; i = i + 1) begin
+      vip_mst.AXI4LITE_WRITE_BURST(16'h001C, 0, i, resp);  // Load Chirp Sequence
+    end
+    for (int i = 0; i < 8; i = i + 1) begin
+      vip_mst.AXI4LITE_WRITE_BURST(16'h001C, 0, i, resp);  // Load Chirp Sequence
+    end
+
+    // Load Start Phases
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0020, 0, 0, resp);  // Set Start Address
+    for (int i = 0; i < 8; i = i + 1) begin
+      vip_mst.AXI4LITE_WRITE_BURST(16'h0024, 0, i, resp);  // Load Chirp Sequence
+    end    
+
+    for (int i = 0; i < n_pulses; i = i + 1) begin
+
+      repeat(1000) @(posedge clk);
+      start_pulse = 1'b1;
+      @(posedge clk);
+      start_pulse = 1'b0;
+
+      repeat(n_samp_per_chip * n_chip_per_pulse) @(posedge clk);
+    end


-    repeat(25) @(posedge clk);
-    start_pulse = 1'b1;
-    @(posedge clk);
-    start_pulse = 1'b0;
-
+    repeat(10000) @(posedge clk);
+    $fclose(fid_out);
+    $display($time, " << Ending the Simulation >>");
+    $stop; 

 end

+// Write output data to file
 always @ (posedge clk) begin
    if ( iq_out_valid == 1'b1 ) begin
        $fwrite(fid_out, "%d\n", iq_out[15:0] );
--- a/radar_alinx_kintex.srcs/sources_1/sim/tb_timing_engine.sv
+++ b/radar_alinx_kintex.srcs/sources_1/sim/tb_timing_engine.sv
@@ -0,0 +1,111 @@
+`timescale 1ns / 1ps
+
+import axi_vip_pkg::*;
+import axi_vip_0_pkg::*;
+
+module testbench();
+
+
+reg clk;
+reg reset;
+reg resetn;
+
+assign resetn = ~reset;
+
+localparam T = 4;
+always #(T/2) clk=~clk;
+
+axi4l_intf # (
+  .AXI_ADDR_WIDTH(32), 
+  .AXI_DATA_WIDTH(32)
+) 
+ctrl_if (
+  .clk(clk),
+  .resetn(resetn)
+);
+
+axi_vip_0_mst_t  vip_mst;
+xil_axi_resp_t     resp;
+
+axi_vip_0 axi_vip_inst (
+  .aclk(clk),                   
+  .aresetn(resetn),             
+  .m_axi_awaddr( ctrl_if.awaddr ),
+  .m_axi_awprot( ctrl_if.awprot ),
+  .m_axi_awvalid( ctrl_if.awvalid ),
+  .m_axi_awready( ctrl_if.awready ),
+  .m_axi_wdata( ctrl_if.wdata ),
+  .m_axi_wstrb( ctrl_if.wstrb ),
+  .m_axi_wvalid( ctrl_if.wvalid ),
+  .m_axi_wready( ctrl_if.wready ),
+  .m_axi_bresp( ctrl_if.bresp ),
+  .m_axi_bvalid( ctrl_if.bvalid ),
+  .m_axi_bready( ctrl_if.bready ),
+  .m_axi_araddr( ctrl_if.araddr ),
+  .m_axi_arprot( ctrl_if.arprot ),
+  .m_axi_arvalid( ctrl_if.arvalid ),
+  .m_axi_arready( ctrl_if.arready ),
+  .m_axi_rdata( ctrl_if.rdata ),
+  .m_axi_rresp( ctrl_if.rresp ),
+  .m_axi_rvalid( ctrl_if.rvalid ),
+  .m_axi_rready( ctrl_if.rready )  
+
+);
+
+initial begin
+    vip_mst = new("vip_mst", axi_vip_inst.inst.IF);
+    vip_mst.start_master();
+end
+
+axi4s_intf # (
+    .AXI_DATA_WIDTH(64),
+    .AXI_USER_WIDTH(16)
+) 
+hdr_out[2] ();      
+
+timing_engine dut (
+  .clk(clk),    
+  .pps(1'b0),
+
+  .ctrl_if(ctrl_if),
+  .start_of_cpi(),
+  .start_of_pulse(),
+  .timing_pulses(),
+  .hdr_out(hdr_out)
+);
+
+int fid_out;
+
+initial begin
+    reset = 1'b1;
+    clk = 1'b0;
+    $display($time, " << Starting the Simulation >>");
+
+    // Release Reset
+    repeat(25) @(posedge clk);
+    reset = 1'b0;
+    repeat(25) @(posedge clk);
+
+    // Set Control Regs
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 1, resp);   
+
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 16, resp);   
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, 4, resp);             
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0010, 0, 10, resp);
+
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0080, 0, 3, resp);       
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0084, 0, 4, resp);       
+
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0088, 0, 8, resp);       
+    vip_mst.AXI4LITE_WRITE_BURST(16'h008C, 0, 5, resp);          
+
+    vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 0, resp);   
+
+    repeat(10000) @(posedge clk);
+    $display($time, " << Ending the Simulation >>");
+    $stop; 
+
+end
+
+endmodule
+`resetall
--- a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
+++ b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
--- a/radar_alinx_kintex.xpr
+++ b/radar_alinx_kintex.xpr
@@ -56,20 +56,20 @@
    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
    <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="WTXSimLaunchSim" Val="34"/>
+    <Option Name="WTXSimLaunchSim" Val="110"/>
    <Option Name="WTModelSimLaunchSim" Val="0"/>
    <Option Name="WTQuestaLaunchSim" Val="0"/>
    <Option Name="WTIesLaunchSim" Val="0"/>
    <Option Name="WTVcsLaunchSim" Val="0"/>
    <Option Name="WTRivieraLaunchSim" Val="0"/>
    <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="53"/>
-    <Option Name="WTModelSimExportSim" Val="53"/>
-    <Option Name="WTQuestaExportSim" Val="53"/>
+    <Option Name="WTXSimExportSim" Val="60"/>
+    <Option Name="WTModelSimExportSim" Val="60"/>
+    <Option Name="WTQuestaExportSim" Val="60"/>
    <Option Name="WTIesExportSim" Val="0"/>
-    <Option Name="WTVcsExportSim" Val="53"/>
-    <Option Name="WTRivieraExportSim" Val="53"/>
-    <Option Name="WTActivehdlExportSim" Val="53"/>
+    <Option Name="WTVcsExportSim" Val="60"/>
+    <Option Name="WTRivieraExportSim" Val="60"/>
+    <Option Name="WTActivehdlExportSim" Val="60"/>
    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
    <Option Name="XSimRadix" Val="hex"/>
    <Option Name="XSimTimeUnit" Val="ns"/>
@@ -451,49 +451,63 @@
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PSRCDIR/sources_1/hdl/digital_rx_chain.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/delay_shift_reg.sv">
+        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PSRCDIR/sources_1/hdl/ethernet_top.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/digital_rx_chain.sv">
+        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PSRCDIR/sources_1/hdl/timing_engine.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/ethernet_top.sv">
+        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PSRCDIR/sources_1/hdl/util_reg.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_ofdm.sv">
+        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PSRCDIR/sources_1/hdl/waveform_gen.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_sine.sv">
+        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PSRCDIR/sources_1/hdl/top.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/timing_engine.sv">
+        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PSRCDIR/sources_1/ip/clock_converter/clock_converter.xci">
+      <File Path="$PSRCDIR/sources_1/hdl/util_reg.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/hdl/top.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/ip/width_converter/width_converter.xci">
        <FileInfo>
          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
@@ -509,7 +523,7 @@
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PSRCDIR/sources_1/ip/width_converter/width_converter.xci">
+      <File Path="$PSRCDIR/sources_1/ip/clock_converter/clock_converter.xci">
        <FileInfo>
          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
@@ -517,15 +531,7 @@
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_sine.sv">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_ofdm.sv">
+      <File Path="$PSRCDIR/sources_1/hdl/waveform_gen.sv">
        <FileInfo>
          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
@@ -555,8 +561,16 @@
    </FileSet>
    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/sim/tb_timing_engine.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
      <File Path="$PSRCDIR/sources_1/sim/tb_gen_ofdm.sv">
        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
@@ -578,14 +592,6 @@
    </FileSet>
    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
      <Filter Type="Utils"/>
-      <File Path="$PSRCDIR/utils_1/imports/synth_1/top.dcp">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedInSteps" Val="synth_1"/>
-          <Attr Name="AutoDcp" Val="1"/>
-        </FileInfo>
-      </File>
      <File Path="$PSRCDIR/set_build_date.tcl">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
@@ -699,6 +705,7 @@
    <FileSet Name="wf_memory" Type="BlockSrcs" RelSrcDir="$PSRCDIR/wf_memory" RelGenDir="$PGENDIR/wf_memory">
      <File Path="$PSRCDIR/sources_1/ip/wf_memory/wf_memory.xci">
        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
@@ -785,7 +792,6 @@
    <FileSet Name="wfg_cordic" Type="BlockSrcs" RelSrcDir="$PSRCDIR/wfg_cordic" RelGenDir="$PGENDIR/wfg_cordic">
      <File Path="$PSRCDIR/sources_1/ip/wfg_cordic/wfg_cordic.xci">
        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
@@ -812,6 +818,34 @@
        <Option Name="UseBlackboxStub" Val="1"/>
      </Config>
    </FileSet>
+    <FileSet Name="ofdm_sequence_ram" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ofdm_sequence_ram" RelGenDir="$PGENDIR/ofdm_sequence_ram">
+      <File Path="$PSRCDIR/sources_1/ip/ofdm_sequence_ram/ofdm_sequence_ram.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="ofdm_sequence_ram"/>
+        <Option Name="dataflowViewerSettings" Val="min_width=16"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="freq_mult" Type="BlockSrcs" RelSrcDir="$PSRCDIR/freq_mult" RelGenDir="$PGENDIR/freq_mult">
+      <File Path="$PSRCDIR/sources_1/ip/freq_mult/freq_mult.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="freq_mult"/>
+        <Option Name="dataflowViewerSettings" Val="min_width=16"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
  </FileSets>
  <Simulators>
    <Simulator Name="XSim">
@@ -835,7 +869,7 @@
    </Simulator>
  </Simulators>
  <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
        <Step Id="synth_design" PreStepTclHook="$PSRCDIR/set_build_date.tcl"/>
@@ -915,12 +949,11 @@
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
    </Run>
-    <Run Id="wf_memory_synth_1" Type="Ft3:Synth" SrcSet="wf_memory" Part="xcku040-ffva1156-2-i" ConstrsSet="wf_memory" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/wf_memory_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1">
+    <Run Id="wf_memory_synth_1" Type="Ft3:Synth" SrcSet="wf_memory" Part="xcku040-ffva1156-2-i" ConstrsSet="wf_memory" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wf_memory_synth_1">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
        <Step Id="synth_design"/>
      </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
@@ -935,12 +968,11 @@
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
    </Run>
-    <Run Id="pulse_buffer_204B_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_204B_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_204B_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pulse_buffer_204B_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_204B_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_204B_fifo_synth_1">
+    <Run Id="pulse_buffer_204B_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_204B_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_204B_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_204B_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_204B_fifo_synth_1">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
        <Step Id="synth_design"/>
      </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
@@ -955,12 +987,11 @@
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
    </Run>
-    <Run Id="jesd_core_clk_wiz_synth_1" Type="Ft3:Synth" SrcSet="jesd_core_clk_wiz" Part="xcku040-ffva1156-2-i" ConstrsSet="jesd_core_clk_wiz" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/jesd_core_clk_wiz_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/jesd_core_clk_wiz_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/jesd_core_clk_wiz_synth_1">
+    <Run Id="jesd_core_clk_wiz_synth_1" Type="Ft3:Synth" SrcSet="jesd_core_clk_wiz" Part="xcku040-ffva1156-2-i" ConstrsSet="jesd_core_clk_wiz" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/jesd_core_clk_wiz_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/jesd_core_clk_wiz_synth_1">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
        <Step Id="synth_design"/>
      </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
@@ -995,6 +1026,26 @@
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
    </Run>
+    <Run Id="ofdm_sequence_ram_synth_1" Type="Ft3:Synth" SrcSet="ofdm_sequence_ram" Part="xcku040-ffva1156-2-i" ConstrsSet="ofdm_sequence_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ofdm_sequence_ram_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="freq_mult_synth_1" Type="Ft3:Synth" SrcSet="freq_mult" Part="xcku040-ffva1156-2-i" ConstrsSet="freq_mult" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/freq_mult_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/freq_mult_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/freq_mult_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
@@ -1268,6 +1319,40 @@
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
    </Run>
+    <Run Id="ofdm_sequence_ram_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="ofdm_sequence_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ofdm_sequence_ram_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="freq_mult_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="freq_mult" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="freq_mult_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/freq_mult_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/freq_mult_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
  </Runs>
  <MsgRule>
    <MsgAttr Name="RuleType" Val="0"/>
--- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a
+++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a
--- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/liblwip4.a
+++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/liblwip4.a
--- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a
+++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a
--- a/vitis/top/microblaze_0/standalone_microblaze_0/bsp/microblaze_0/lib/libxil.a
+++ b/vitis/top/microblaze_0/standalone_microblaze_0/bsp/microblaze_0/lib/libxil.a
--- a/vitis/top/platform.tcl
+++ b/vitis/top/platform.tcl
@@ -236,3 +236,6 @@ bsp write
 bsp reload
 catch {bsp regenerate}
 platform generate -domains freertos10_xilinx_microblaze_0 
+platform clean
+platform clean
+platform clean
Author	SHA1	Message	Date
bkiedinger@gmail.com	ef68f51d09	fixing pulse gen bugs	2025-11-19 20:57:42 -06:00
bkiedinger@gmail.com	5923ec0831	renamed system verilog files to have .sv extensions	2025-11-12 21:33:16 -06:00
bkiedinger@gmail.com	d9a14af015	added latency to freq mult to improve timing, had to delete and remake the IP core for some reason	2025-11-12 20:45:54 -06:00
bkiedinger@gmail.com	b0356dba9d	antoehr bug	2025-11-12 09:09:57 -06:00
bkiedinger@gmail.com	ea0785e7d3	fix multidriver net issue in real build that worked fine in simulation	2025-11-12 08:52:44 -06:00
bkiedinger@gmail.com	522bd9e8c9	clean sw to remove unneeded files from git	2025-10-18 12:28:43 -05:00
bkiedinger@gmail.com	bf8afe675e	remove dcp	2025-10-18 12:25:42 -05:00
bkiedinger@gmail.com	653bf70da7	reset project to clean up for castelion git	2025-10-17 11:59:00 -05:00
bkiedinger@gmail.com	60ac0021c8	updates to ofdm waveform gen	2025-10-17 11:52:35 -05:00