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ef68f51d09
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fixing pulse gen bugs
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2025-11-19 20:57:42 -06:00 |
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5923ec0831
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renamed system verilog files to have .sv extensions
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2025-11-12 21:33:16 -06:00 |
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d9a14af015
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added latency to freq mult to improve timing, had to delete and remake the IP core for some reason
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2025-11-12 20:45:54 -06:00 |
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ea0785e7d3
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fix multidriver net issue in real build that worked fine in simulation
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2025-11-12 08:52:44 -06:00 |
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bf8afe675e
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remove dcp
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2025-10-18 12:25:42 -05:00 |
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653bf70da7
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reset project to clean up for castelion git
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2025-10-17 11:59:00 -05:00 |
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60ac0021c8
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updates to ofdm waveform gen
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2025-10-17 11:52:35 -05:00 |
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086c5dd9f3
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starting wfg
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2025-09-28 08:55:19 -05:00 |
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6dfee38d7c
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support for multiple waveforms
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2025-06-29 20:18:52 -05:00 |
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d60c55f292
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decimation working
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2025-06-11 08:36:31 -05:00 |
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316ae900ae
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version number and reverified data recording rate
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2025-06-08 16:34:22 -05:00 |
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6e4aa1230a
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last update to chris
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2025-05-29 20:47:32 -05:00 |
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fcb291590b
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updates
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2025-05-20 20:33:12 -05:00 |
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8a1a6ea770
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this build works at 9 GSPS DAC, 3 GSPS ADC, 750 MSPS IQ
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2025-04-25 06:26:07 -05:00 |
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729d034a13
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fixed pinout, made some updates for discrete timing pulses, needs to be tested
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2025-04-14 08:17:28 -05:00 |
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18988b8656
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gitting project in git
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2025-03-30 21:43:59 -05:00 |
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